This RISC-V implementation is described in the book "Inside An Open-Source Processor" ISBN 978-3-89576-443-1
forked from montedalrymple/yrv
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
License
yuri-panchul/yrv-plus
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
About
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published
Languages
- Verilog 90.6%
- SystemVerilog 4.0%
- Shell 3.5%
- Tcl 1.8%
- Other 0.1%