This is a java app that generates systolic array (SA) verilog code.
Enter the size of systolic array, which is the numbers of PE in the SA, N*N enters N, and the bits of the weight or input register, it will auto generate the SA verilog code and a simple testbench verilog file.
In the initial version, the generator only generates Sparse-TPU PE design, which is an architecture that introduced by He, Xin.