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Python 2 to 3 migration changes: format strings (kevinpt#6)
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Changed all the uses of .format to f-strings instead.

Signed-off-by: Wouter van Verre <woutervanverre@gmail.com>
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@vvvverre
vvvverre committed Feb 1, 2022
1 parent a3614b1 commit c030ea8
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Showing 3 changed files with 32 additions and 29 deletions.
2 changes: 1 addition & 1 deletion minilexer.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ def run(self, text):
m = pat.match(text, pos)
if m:
if action:
log.debug('Match: {} -> {}'.format(m.group().strip(), action))
log.debug(f"Match: {m.group().strip()} -> {action}")

yield (pos, m.end() - 1), action, m.groups()

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10 changes: 5 additions & 5 deletions verilog_parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -80,15 +80,15 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non

def __str__(self):
if self.mode is not None:
param = '{} : {} {}'.format(self.name, self.mode, self.data_type)
param = f"{self.name} : {self.mode} {self.data_type}"
else:
param = '{} : {}'.format(self.name, self.data_type)
param = f"{self.name} : {self.data_type}"
if self.default_value is not None:
param = '{} := {}'.format(param, self.default_value)
param = f"{param} := {self.default_value}"
return param

def __repr__(self):
return "VerilogParameter('{}')".format(self.name)
return f"VerilogParameter('{self.name}')"


class VerilogModule(VerilogObject):
Expand All @@ -103,7 +103,7 @@ def __init__(self, name, ports, generics=None, sections=None, desc=None):
self.sections = sections if sections is not None else {}

def __repr__(self):
return "VerilogModule('{}') {}".format(self.name, self.ports)
return f"VerilogModule('{self.name}') {self.ports}"


def parse_verilog_file(fname):
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49 changes: 26 additions & 23 deletions vhdl_parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,7 @@
(r'\n\s*\)\s*;\s*--(.*)\n', 'port_list_comment', '#pop:2'),
(r'\n\s*', None),
(r'\)\s*;', 'end_port', '#pop:2'),

(r'--#(.*)\n', 'metacomment'),
(r'/\*', 'block_comment', 'block_comment'),
],
Expand Down Expand Up @@ -193,18 +194,20 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non

def __str__(self):
if self.mode is not None:
param = '{} : {} {}'.format(self.name, self.mode, self.data_type.name + self.data_type.arange)
param = f"{self.name} : {self.mode} {self.data_type.name + self.data_type.arange}"
else:
param = '{} : {}'.format(self.name, self.data_type.name + self.data_type.arange)
param = f"{self.name} : {self.data_type.name + self.data_type.arange}"

if self.default_value is not None:
param = '{} := {}'.format(param, self.default_value)
param = f"{param} := {self.default_value}"

if self.param_desc is not None:
param = '{} --{}'.format(param, self.param_desc)
param = f"{param} --{self.param_desc}"

return param

def __repr__(self):
return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode,
self.data_type.name + self.data_type.arange)
return f"VhdlParameter('{self.name}', '{self.mode}', '{self.data_type.name + self.data_type.arange}')"


class VhdlParameterType:
Expand All @@ -226,7 +229,7 @@ def __init__(self, name, direction="", r_bound="", l_bound="", arange=""):
self.arange = arange

def __repr__(self):
return "VhdlParameterType('{}','{}')".format(self.name, self.arange)
return f"VhdlParameterType('{self.name}','{self.arange}')"


class VhdlPackage(VhdlObject):
Expand Down Expand Up @@ -259,7 +262,7 @@ def __init__(self, name, package, type_of, desc=None):
self.type_of = type_of

def __repr__(self):
return "VhdlType('{}', '{}')".format(self.name, self.type_of)
return f"VhdlType('{self.name}', '{self.type_of}')"


class VhdlSubtype(VhdlObject):
Expand All @@ -279,7 +282,7 @@ def __init__(self, name, package, base_type, desc=None):
self.base_type = base_type

def __repr__(self):
return "VhdlSubtype('{}', '{}')".format(self.name, self.base_type)
return f"VhdlSubtype('{self.name}', '{self.base_type}')"


class VhdlConstant(VhdlObject):
Expand All @@ -299,7 +302,7 @@ def __init__(self, name, package, base_type, desc=None):
self.base_type = base_type

def __repr__(self):
return "VhdlConstant('{}', '{}')".format(self.name, self.base_type)
return f"VhdlConstant('{self.name}', '{self.base_type}')"


class VhdlFunction(VhdlObject):
Expand All @@ -321,7 +324,7 @@ def __init__(self, name, package, parameters, return_type=None, desc=None):
self.return_type = return_type

def __repr__(self):
return "VhdlFunction('{}')".format(self.name)
return f"VhdlFunction('{self.name}')"


class VhdlProcedure(VhdlObject):
Expand All @@ -341,7 +344,7 @@ def __init__(self, name, package, parameters, desc=None):
self.parameters = parameters

def __repr__(self):
return "VhdlProcedure('{}')".format(self.name)
return f"VhdlProcedure('{self.name}')"


class VhdlEntity(VhdlObject):
Expand All @@ -362,12 +365,12 @@ def __init__(self, name, ports, generics=None, sections=None, desc=None):
self.sections = sections if sections is not None else {}

def __repr__(self):
return "VhdlEntity('{}')".format(self.name)
return f"VhdlEntity('{self.name}')"

def dump(self):
print('VHDL entity: {}'.format(self.name))
print(f"VHDL entity: {self.name}")
for p in self.ports:
print('\t{} ({}), {} ({})'.format(p.name, type(p.name), p.data_type, type(p.data_type)))
print(f"\t{p.name} ({type(p.name)}), {p.data_type} ({type(p.data_type)})")


class VhdlComponent(VhdlObject):
Expand All @@ -391,12 +394,12 @@ def __init__(self, name, package, ports, generics=None, sections=None, desc=None
self.sections = sections if sections is not None else {}

def __repr__(self):
return "VhdlComponent('{}')".format(self.name)
return f"VhdlComponent('{self.name}')"

def dump(self):
print('VHDL component: {}'.format(self.name))
print(f"VHDL component: {self.name}")
for p in self.ports:
print('\t{} ({}), {} ({})'.format(p.name, type(p.name), p.data_type, type(p.data_type)))
print(f"\t{p.name} ({type(p.name)}), {p.data_type} ({type(p.data_type)})")


def parse_vhdl_file(fname):
Expand Down Expand Up @@ -641,12 +644,12 @@ def subprogram_prototype(vo):

if isinstance(vo, VhdlFunction):
if len(vo.parameters) > 0:
proto = 'function {}({}) return {};'.format(vo.name, plist, vo.return_type)
proto = f"function {vo.name}({plist}) return {vo.return_type};"
else:
proto = 'function {} return {};'.format(vo.name, vo.return_type)
proto = f"function {vo.name} return {vo.return_type};"

else: # procedure
proto = 'procedure {}({});'.format(vo.name, plist)
proto = f"procedure {vo.name}({plist});"

return proto

Expand All @@ -665,10 +668,10 @@ def subprogram_signature(vo, fullname=None):

if isinstance(vo, VhdlFunction):
plist = ','.join(p.data_type for p in vo.parameters)
sig = '{}[{} return {}]'.format(fullname, plist, vo.return_type)
sig = f"{fullname}[{plist} return {vo.return_type}]"
else: # procedure
plist = ','.join(p.data_type for p in vo.parameters)
sig = '{}[{}]'.format(fullname, plist)
sig = f"{fullname}[{plist}]"

return sig

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