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Synopsys
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cpp-lru-cache
cpp-lru-cache PublicForked from lamerman/cpp-lru-cache
Simple and reliable LRU cache for c++ based on hashmap and linkedlist
C++
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axi_mem_if
axi_mem_if PublicForked from pulp-platform/axi_mem_if
Simple single-port AXI memory interface
SystemVerilog
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axi4-interface
axi4-interface PublicForked from mmxsrup/axi4-interface
AXI4 and AXI4-Lite interface definitions
SystemVerilog
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AXI_Slave_Interface
AXI_Slave_Interface PublicForked from thejokerlol/AXI_Slave_Interface
A Slave interface for DRAM
Verilog
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verilator
verilator PublicForked from verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
C++
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