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rtl: fix rst instruction
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zephray committed Mar 30, 2019
1 parent dd50586 commit ea58fc1
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Showing 5 changed files with 37 additions and 8 deletions.
5 changes: 5 additions & 0 deletions .gitignore
Expand Up @@ -61,6 +61,11 @@ impact*
*.asc
*.onl

# Test
*.vcd
*.actual
*.expected

# binary files
*.gb

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Binary file modified doc/control_unit.ods
Binary file not shown.
2 changes: 1 addition & 1 deletion rtl/alu.v
Expand Up @@ -102,7 +102,7 @@ module alu(
~({1'b0, alu_b[7:4]}) +
{4'b0, ~result_low[4]};
alu_flags_out[F_C] = result_high[4];
alu_result = (alu_op == OP_CP) ? (alu_b[7:0]) : {result_high[3:0], result_low[3:0]};
alu_result = (alu_op == OP_CP) ? (alu_a[7:0]) : {result_high[3:0], result_low[3:0]};
alu_flags_out[F_Z] = ({result_high[3:0], result_low[3:0]} == 8'd0) ? 1'b1 : 1'b0;
end
OP_AND: begin
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32 changes: 28 additions & 4 deletions rtl/control.v
Expand Up @@ -200,6 +200,22 @@ module control(
// RETI
ime_clear = 1'b1;
end
else if ((opcode == 8'h07) ||
(opcode == 8'h17) ||
(opcode == 8'h0F) ||
(opcode == 8'h1F)) begin
flags_pattern = 2'b10;
end
else if ((opcode == 8'hC7) ||
(opcode == 8'hD7) ||
(opcode == 8'hE7) ||
(opcode == 8'hF7) ||
(opcode == 8'hCF) ||
(opcode == 8'hEF) ||
(opcode == 8'hDF) ||
(opcode == 8'hFF)) begin
//bus_op = 2'b10;
end
else if ((opcode == 8'h04) ||
(opcode == 8'h14) ||
(opcode == 8'h24) ||
Expand Down Expand Up @@ -229,8 +245,15 @@ module control(
(opcode == 8'h9B) ||
(opcode == 8'h9C) ||
(opcode == 8'h9D) ||
(opcode == 8'h9F)) begin
// SUB
(opcode == 8'h9F) ||
(opcode == 8'hB8) ||
(opcode == 8'hB9) ||
(opcode == 8'hBA) ||
(opcode == 8'hBB) ||
(opcode == 8'hBC) ||
(opcode == 8'hBD) ||
(opcode == 8'hBF)) begin
// SUB, CP
alu_src_xchg = 1'b1;
end
else if ((opcode == 8'h86) ||
Expand Down Expand Up @@ -436,8 +459,8 @@ module control(
rf_wr_sel = 3'b111;
rf_rd_sel = 3'b101;
end
else if ((opcode == 8'h96) || (opcode == 8'h9E) || (opcode == 8'hD6) || (opcode == 8'hDE)) begin
// SUB [HL] or SUB n
else if ((opcode == 8'h96) || (opcode == 8'h9E) || (opcode == 8'hD6) || (opcode == 8'hDE) || (opcode == 8'hBE) || (opcode == 8'hFE)) begin
// SUB [HL], SUB n, CP [HL], CP n
alu_src_xchg = 1;
end
else if (opcode == 8'hCB) begin
Expand Down Expand Up @@ -536,6 +559,7 @@ module control(
pc_src = 2'b01;
pc_we = 1'b1;
bus_op = 2'b10;
ct_op = 2'b00;
next = 1'b1;
end
else if (((opcode == 8'hC4) && (!f_z)) || // CALL NZ
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6 changes: 3 additions & 3 deletions rtl/ppu.v
Expand Up @@ -330,7 +330,7 @@ module ppu(
// Data that will be pushed into pixel FIFO
// Organized in pixels
reg [31:0] current_fetch_result;
always@(current_tile_data_1, current_tile_data_0) begin
always@(*) begin
for (i = 0; i < 8; i = i + 1) begin
current_fetch_result[i*4+3] = current_tile_data_1[i];
current_fetch_result[i*4+2] = current_tile_data_0[i];
Expand Down Expand Up @@ -359,7 +359,7 @@ module ppu(
// Cascade mux used to implement the searching of next id would be triggered
reg [3:0] obj_trigger_id_from[0:10];
reg [3:0] obj_trigger_id_next;
always@(h_pix_obj, obj_trigger_id) begin
always@(*) begin
obj_trigger_id_from[10] = OBJ_TRIGGER_NOT_FOUND; // There is no more after the 10th
for (i = 9; i >= 0; i = i - 1) begin
obj_trigger_id_from[i] =
Expand Down Expand Up @@ -553,7 +553,7 @@ module ppu(
end

reg [31:0] half_merge_result;
always @(current_fetch_result, pf_data) begin
always @(*) begin
for (i = 0; i < 8; i = i + 1) begin
if ((pf_data[32+i*4+1] == PPU_PAL_BG[1])&&(pf_data[32+i*4+0] == PPU_PAL_BG[0])) begin
half_merge_result[i*4+3] = current_fetch_result[i*4+3];
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