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gas: arm: Fix a further IT-predicated vcvt issue in the presense of M…
…VE vcvtn Previously we had experienced issues with assembling a "VCVTNE" instruction in the presence of the MVE architecture extension, because it could be interpreted both as: * The base instruction VCVT + NE for IT predication when inside an IT block. * The MVE instruction VCVTN + E in the Else of a VPT block. Given a C reproducer of: ``` int test_function(float value) { int ret_val = 10; if (value != 0.0) { ret_val = (int) value; } return ret_val; } ``` GCC generates a VCVTNE instruction based on the `truncsisf2_vfp` pattern, which will look like: `vcvtne.s32.f32 s-reg, s-reg` This still triggers an error due to being misidentified as "vcvtn+e" Similar errors were found with other type combinations and instruction patterns (these have all been added to the testing of this patch). This class of errors was previously worked around by: https://sourceware.org/pipermail/binutils/2020-August/112728.html which addressed this by looking at the operand types, however, that isn't adequate to cover all the extra cases that have been found. Instead, we add some special-casing logic earlier when the instructions are parsed that is conditional on whether we are in a VPT block or not, when the instruction is parsed. gas/ChangeLog: * config/tc-arm.c (opcode_lookup): Add special vcvtn handling. * testsuite/gas/arm/mve-vcvtne-it-bad.l: Add further testing. * testsuite/gas/arm/mve-vcvtne-it-bad.s: Likewise. * testsuite/gas/arm/mve-vcvtne-it.d: Likewise. * testsuite/gas/arm/mve-vcvtne-it.s: Likewise. (cherry picked from commit 656412a) Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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[^:]*: Assembler messages: | ||
[^:]*:3: Error: thumb conditional instruction should be in IT block -- `vcvtne.s32.f64 s13,d8' | ||
[^:]*:4: Error: thumb conditional instruction should be in IT block -- `vcvtne.u32.f64 s13,d8' | ||
[^:]*:5: Error: thumb conditional instruction should be in IT block -- `vcvtne.s32.f32 s13,s8' | ||
[^:]*:6: Error: thumb conditional instruction should be in IT block -- `vcvtne.u32.f32 s13,s8' | ||
[^:]*:7: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
[^:]*:7: Error: thumb conditional instruction should be in IT block -- `vcvtne.s32.f16 s13,s8' | ||
[^:]*:8: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
[^:]*:8: Error: thumb conditional instruction should be in IT block -- `vcvtne.u32.f16 s13,s8' | ||
[^:]*:9: Error: thumb conditional instruction should be in IT block -- `vcvtne.f64.s32 d13,s8' | ||
[^:]*:10: Error: thumb conditional instruction should be in IT block -- `vcvtne.f64.u32 d13,s8' | ||
[^:]*:11: Error: thumb conditional instruction should be in IT block -- `vcvtne.f32.s32 s13,s8' | ||
[^:]*:12: Error: thumb conditional instruction should be in IT block -- `vcvtne.f32.u32 s13,s8' | ||
[^:]*:13: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
[^:]*:13: Error: thumb conditional instruction should be in IT block -- `vcvtne.f16.s32 s13,s8' | ||
[^:]*:14: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
[^:]*:14: Error: thumb conditional instruction should be in IT block -- `vcvtne.f16.u32 s13,s8' |
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.syntax unified | ||
.text | ||
vcvtne.s32.f64 s13, d8 | ||
vcvtne.u32.f64 s13, d8 | ||
vcvtne.s32.f32 s13, s8 | ||
vcvtne.u32.f32 s13, s8 | ||
vcvtne.s32.f16 s13, s8 | ||
vcvtne.u32.f16 s13, s8 | ||
vcvtne.f64.s32 d13, s8 | ||
vcvtne.f64.u32 d13, s8 | ||
vcvtne.f32.s32 s13, s8 | ||
vcvtne.f32.u32 s13, s8 | ||
vcvtne.f16.s32 s13, s8 | ||
vcvtne.f16.u32 s13, s8 |
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# name: Armv8.1-M Mainline vcvt instruction in it block (with MVE) | ||
# as: -march=armv8.1-m.main+mve.fp+fp.dp | ||
#warning: [^:]*: Assembler messages: | ||
#warning: [^:]*:10: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
#warning: [^:]*:11: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
#warning: [^:]*:19: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
#warning: [^:]*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE | ||
# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main | ||
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.*: +file format .*arm.* | ||
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Disassembly of section .text: | ||
^[^>]*> bf18[ ]+it[ ]+ne | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eefd 6bc8[ ]+vcvtne.s32.f64[ ]+s13, d8 | ||
^[^>]*> eefc 6bc8[ ]+vcvtne.u32.f64[ ]+s13, d8 | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eefd 6ac4[ ]+vcvtne.s32.f32[ ]+s13, s8 | ||
^[^>]*> eefc 6ac4[ ]+vcvtne.u32.f32[ ]+s13, s8 | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eefd 69c4[ ]+vcvtne.s32.f16[ ]+s13, s8.* | ||
^[^>]*> eefc 69c4[ ]+vcvtne.u32.f16[ ]+s13, s8.* | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eeb8 dbc4[ ]+vcvtne.f64.s32[ ]+d13, s8 | ||
^[^>]*> eeb8 db44[ ]+vcvtne.f64.u32[ ]+d13, s8 | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eef8 6ac4[ ]+vcvtne.f32.s32[ ]+s13, s8 | ||
^[^>]*> eef8 6a44[ ]+vcvtne.f32.u32[ ]+s13, s8 | ||
^[^>]*> bf1c[ ]+itt[ ]+ne | ||
^[^>]*> eef8 69c4[ ]+vcvtne.f16.s32[ ]+s13, s8.* | ||
^[^>]*> eef8 6944[ ]+vcvtne.f16.u32[ ]+s13, s8.* | ||
#pass |
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@@ -1,4 +1,20 @@ | ||
.syntax unified | ||
.text | ||
it ne | ||
itt ne | ||
vcvtne.s32.f64 s13, d8 | ||
vcvtne.u32.f64 s13, d8 | ||
itt ne | ||
vcvtne.s32.f32 s13, s8 | ||
vcvtne.u32.f32 s13, s8 | ||
itt ne | ||
vcvtne.s32.f16 s13, s8 | ||
vcvtne.u32.f16 s13, s8 | ||
itt ne | ||
vcvtne.f64.s32 d13, s8 | ||
vcvtne.f64.u32 d13, s8 | ||
itt ne | ||
vcvtne.f32.s32 s13, s8 | ||
vcvtne.f32.u32 s13, s8 | ||
itt ne | ||
vcvtne.f16.s32 s13, s8 | ||
vcvtne.f16.u32 s13, s8 |