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INT CNTRL: Generalize to N controllers
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Each controller is mapped to its respective
CPU one to one.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
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@aescolar
aescolar committed Sep 1, 2023
1 parent 1ea8194 commit 57b61a9
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Showing 16 changed files with 463 additions and 293 deletions.
122 changes: 122 additions & 0 deletions src/HW_models/NHW_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,54 @@
#define NHW_GPIOTE_0 0
#define NHW_GPIOTE_INT_MAP {{0 , 6}} /*Only core,GPIOTE_IRQn*/

#define NHW_INTCTRL_TOTAL_INST 1
#define NHW_INTCTRL_MAX_INTLINES 48

/* These names are taken from the IRQn_Type in the MDK header */
#define NHW_INT_NAMES { [0] = {\
[0 ] = "POWER_CLOCK",\
[1 ] = "RADIO",\
[2 ] = "UARTE0_UART0",\
[3 ] = "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0",\
[4 ] = "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1",\
[5 ] = "NFCT",\
[6 ] = "GPIOTE",\
[7 ] = "SAADC",\
[8 ] = "TIMER0",\
[9 ] = "TIMER1",\
[10] = "TIMER2",\
[11] = "RTC0",\
[12] = "TEMP",\
[13] = "RNG",\
[14] = "ECB",\
[15] = "CCM_AAR",\
[16] = "WDT",\
[17] = "RTC1",\
[18] = "QDEC",\
[19] = "COMP_LPCOMP",\
[20] = "SWI0_EGU0",\
[21] = "SWI1_EGU1",\
[22] = "SWI2_EGU2",\
[23] = "SWI3_EGU3",\
[24] = "SWI4_EGU4",\
[25] = "SWI5_EGU5",\
[26] = "TIMER3",\
[27] = "TIMER4",\
[28] = "PWM0",\
[29] = "PDM",\
[32] = "MWU",\
[33] = "PWM1",\
[34] = "PWM2",\
[35] = "SPIM2_SPIS2_SPI2",\
[36] = "RTC2",\
[37] = "I2S",\
[38] = "FPU",\
[39] = "USBD",\
[40] = "UARTE1",\
[45] = "PWM3",\
[47] = "SPIM3",\
}}

#define NHW_RADIO_TOTAL_INST 1
#define NHW_RADIO_0 0
#define NHW_RADIO_INT_MAP {{0 , 1}} /*Only core,RADIO_IRQn*/
Expand Down Expand Up @@ -94,6 +142,8 @@
{0 , 27}, \
} /*Only core,TIMER0..4_IRQn*/

#define NHW_BSTICKER_TOTAL_INST 1
#define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/

#define NHW_FAKE_TIMER_TOTAL_INST 1
#define NHW_FAKE_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/
Expand All @@ -120,6 +170,74 @@
#define NHW_DPPI_N_CH {32, 32} /* Number of channels in each DPPI */
#define NHW_DPPI_N_CHG {6, 6} /* Number of channel groups in each DPPI */

#define NHW_INTCTRL_TOTAL_INST 2
#define NHW_INTCTRL_MAX_INTLINES 58

/* These names are taken from the IRQn_Type in the MDK header */
#define NHW_INT_NAMES { [0 /*Application core*/] = {\
[0 ]= "FPU",\
[1 ]= "CACHE",\
[3 ]= "SPU",\
[5 ]= "CLOCK_POWER",\
[8 ]= "SERIAL0",\
[9 ]= "SERIAL1",\
[10]= "SPIM4",\
[11]= "SERIAL2",\
[12]= "SERIAL3",\
[13]= "GPIOTE0",\
[14]= "SAADC",\
[15]= "TIMER0",\
[16]= "TIMER1",\
[17]= "TIMER2",\
[20]= "RTC0",\
[21]= "RTC1",\
[24]= "WDT0",\
[25]= "WDT1",\
[26]= "COMP_LPCOMP",\
[27]= "EGU0",\
[28]= "EGU1",\
[29]= "EGU2",\
[30]= "EGU3",\
[31]= "EGU4",\
[32]= "EGU5",\
[33]= "PWM0",\
[34]= "PWM1",\
[35]= "PWM2",\
[36]= "PWM3",\
[38]= "PDM0",\
[40]= "I2S0",\
[42]= "IPC",\
[43]= "QSPI",\
[45]= "NFCT",\
[47]= "GPIOTE1",\
[51]= "QDEC0",\
[52]= "QDEC1",\
[54]= "USBD",\
[55]= "USBREGULATOR",\
[57]= "KMU",\
/*[68]= "CRYPTOCELL",*/\
}, [1 /*Network core*/] = {\
[5 ] = "CLOCK_POWER",\
[8 ] = "RADIO",\
[9 ] = "RNG",\
[10] = "GPIOTE",\
[11] = "WDT",\
[12] = "TIMER0",\
[13] = "ECB",\
[14] = "AAR_CCM",\
[16] = "TEMP",\
[17] = "RTC0",\
[18] = "IPC",\
[19] = "SERIAL0",\
[20] = "EGU0",\
[22] = "RTC1",\
[24] = "TIMER1",\
[25] = "TIMER2",\
[26] = "SWI0",\
[27] = "SWI1",\
[28] = "SWI2",\
[29] = "SWI3",\
}}

#define NHW_RNG_TOTAL_INST 1
#define NHW_RNG_NET_0 0
Expand All @@ -133,6 +251,10 @@
#define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \
{1 , 0}} /*App core & Net core, -*/

#define NHW_BSTICKER_TOTAL_INST 2
#define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \
{1 , 0}} /*App core & Net core, -*/

#else
#error "No valid platform was selected"
#endif
Expand Down
6 changes: 3 additions & 3 deletions src/HW_models/NRF_AAR.c
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ static void signal_EVENTS_END(void) {

unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENSET_END_Msk){
nhw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
}
Expand All @@ -63,7 +63,7 @@ static void signal_EVENTS_RESOLVED(void) {

unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENCLR_RESOLVED_Msk){
nhw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
}
Expand All @@ -74,7 +74,7 @@ static void signal_EVENTS_NOTRESOLVED(void) {

unsigned int inst = 0;
if (AAR_INTEN & AAR_INTENCLR_NOTRESOLVED_Msk){
nhw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_aar_irq_map[inst].cntl_inst,
nhw_aar_irq_map[inst].int_nbr);
}
}
Expand Down
6 changes: 3 additions & 3 deletions src/HW_models/NRF_AES_CCM.c
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Original file line number Diff line number Diff line change
Expand Up @@ -198,7 +198,7 @@ static void signal_EVENTS_ENDKSGEN(void) {

int inst = 0;
if (CCM_INTEN & CCM_INTENSET_ENDKSGEN_Msk) {
nhw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
nhw_ccm_irq_map[inst].int_nbr);
}

Expand All @@ -213,7 +213,7 @@ static void signal_EVENTS_ENDCRYPT(void) {

int inst = 0;
if (CCM_INTEN & CCM_INTENSET_ENDCRYPT_Msk) {
nhw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_ccm_irq_map[inst].cntl_inst,
nhw_ccm_irq_map[inst].int_nbr);
}
}
Expand All @@ -223,7 +223,7 @@ static void signal_EVENTS_ENDCRYPT(void) {
NRF_PPI_Event(CCM_EVENTS_ERROR);
if (CCM_INTEN & CCM_INTENSET_ERROR_Msk) {
nhw_irq_ctrl_set_irq(NRF5_IRQ_CCM_AAR_IRQn);
hw_irq_ctrl_set_irq(NRF5_IRQ_CCM_AAR_IRQn);
}
} */

Expand Down
4 changes: 2 additions & 2 deletions src/HW_models/NRF_AES_ECB.c
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Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ static void signal_ENDECB(void) {

int inst = 0;
if (ECB_INTEN & ECB_INTENSET_ENDECB_Msk){
nhw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
nhw_ecb_irq_map[inst].int_nbr);
}
}
Expand All @@ -87,7 +87,7 @@ static void signal_ERRORECB(void) {

int inst = 0;
if (ECB_INTEN & ECB_INTENSET_ERRORECB_Msk){
nhw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
hw_irq_ctrl_set_irq(nhw_ecb_irq_map[inst].cntl_inst,
nhw_ecb_irq_map[inst].int_nbr);
}
}
Expand Down
4 changes: 2 additions & 2 deletions src/HW_models/NRF_CLOCK.c
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Original file line number Diff line number Diff line change
Expand Up @@ -115,11 +115,11 @@ static void nrf_clock_eval_interrupt(void) {
int inst = 0;
if (clock_int_line == false && new_int_line == true) {
clock_int_line = true;
nhw_irq_ctrl_raise_level_irq_line(nhw_clock_irq_map[inst].cntl_inst,
hw_irq_ctrl_raise_level_irq_line(nhw_clock_irq_map[inst].cntl_inst,
nhw_clock_irq_map[inst].int_nbr);
} else if (clock_int_line == true && new_int_line == false) {
clock_int_line = false;
nhw_irq_ctrl_lower_level_irq_line(nhw_clock_irq_map[inst].cntl_inst,
hw_irq_ctrl_lower_level_irq_line(nhw_clock_irq_map[inst].cntl_inst,
nhw_clock_irq_map[inst].int_nbr);
}
}
Expand Down
4 changes: 2 additions & 2 deletions src/HW_models/NRF_EGU.c
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Original file line number Diff line number Diff line change
Expand Up @@ -55,11 +55,11 @@ static void nrf_egu_eval_interrupt(int inst){

if (new_egu_int_line && (egu_int_line[inst] == false)) {
egu_int_line[inst] = true;
nhw_irq_ctrl_raise_level_irq_line(nhw_egu_irq_map[inst].cntl_inst,
hw_irq_ctrl_raise_level_irq_line(nhw_egu_irq_map[inst].cntl_inst,
nhw_egu_irq_map[inst].int_nbr);
} else if ((new_egu_int_line == false) && egu_int_line[inst]) {
egu_int_line[inst] = false;
nhw_irq_ctrl_lower_level_irq_line(nhw_egu_irq_map[inst].cntl_inst,
hw_irq_ctrl_lower_level_irq_line(nhw_egu_irq_map[inst].cntl_inst,
nhw_egu_irq_map[inst].int_nbr);
}
}
Expand Down
4 changes: 2 additions & 2 deletions src/HW_models/NRF_GPIOTE.c
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Original file line number Diff line number Diff line change
Expand Up @@ -134,11 +134,11 @@ static void nrf_gpiote_eval_interrupt(void) {
int inst = 0;
if (gpiote_int_line == false && new_int_line == true) {
gpiote_int_line = true;
nhw_irq_ctrl_raise_level_irq_line(nhw_gpiote_irq_map[inst].cntl_inst,
hw_irq_ctrl_raise_level_irq_line(nhw_gpiote_irq_map[inst].cntl_inst,
nhw_gpiote_irq_map[inst].int_nbr);
} else if (gpiote_int_line == true && new_int_line == false) {
gpiote_int_line = false;
nhw_irq_ctrl_lower_level_irq_line(nhw_gpiote_irq_map[inst].cntl_inst,
hw_irq_ctrl_lower_level_irq_line(nhw_gpiote_irq_map[inst].cntl_inst,
nhw_gpiote_irq_map[inst].int_nbr);
}
}
Expand Down

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