xtensa: add support for dc233c SoC for QEMU

This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

boards/xtensa/qemu_xtensa/Kconfig.board

@@ -1,9 +1,14 @@
 # XTENSA board configuration
 
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2017, 2023 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_QEMU_XTENSA
 	bool "Xtensa emulation using QEMU"
 	depends on SOC_XTENSA_SAMPLE_CONTROLLER
 	select QEMU_TARGET
+
+config BOARD_QEMU_XTENSA_DC233C
+	bool "Xtensa emulation using QEMU (dc233c core)"
+	depends on SOC_XTENSA_DC233C
+	select QEMU_TARGET

boards/xtensa/qemu_xtensa/Kconfig.defconfig

@@ -1,4 +1,4 @@
-# Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2017, 2023 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_QEMU_XTENSA
@@ -13,3 +13,16 @@ config IPM_CONSOLE_STACK_SIZE
 	default 2048 if IPM_CONSOLE_RECEIVER
 
 endif # BOARD_QEMU_XTENSA
+
+if BOARD_QEMU_XTENSA_DC233C
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config BOARD
+	default "qemu_xtensa_dc233c"
+
+config IPM_CONSOLE_STACK_SIZE
+	default 2048 if IPM_CONSOLE_RECEIVER
+
+endif # BOARD_QEMU_XTENSA

boards/xtensa/qemu_xtensa/board.cmake

@@ -2,11 +2,19 @@
 
 set(SUPPORTED_EMU_PLATFORMS qemu)
 
-set(QEMU_CPU_TYPE_${ARCH} sample_controller)
+if(CONFIG_BOARD_QEMU_XTENSA)
+  set(QEMU_CPU_TYPE_${ARCH} sample_controller)
 
-set(QEMU_FLAGS_${ARCH}
-	-machine sim -semihosting -nographic -cpu sample_controller
+  set(QEMU_FLAGS_${ARCH}
+    -machine sim -semihosting -nographic -cpu sample_controller
   )
+elseif(CONFIG_BOARD_QEMU_XTENSA_DC233C)
+  set(QEMU_CPU_TYPE_${ARCH} dc233c)
+
+  set(QEMU_FLAGS_${ARCH}
+    -machine sim -semihosting -nographic -cpu dc233c
+  )
+endif()
 
 # TODO: Support debug
 # board_set_debugger_ifnset(qemu)

boards/xtensa/qemu_xtensa/qemu_xtensa_dc233c.dts

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019, 2023 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "dc233c.dtsi"
+
+/ {
+	model = "qemu_xtensa_dc233c";
+	compatible = "cdns,xtensa-dc233c";
+
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <10000000>;
+};

boards/xtensa/qemu_xtensa/qemu_xtensa_dc233c.yaml

@@ -0,0 +1,11 @@
+identifier: qemu_xtensa_dc233c
+name: QEMU Emulation for Xtensa (dc233c core)
+type: qemu
+simulation: qemu
+arch: xtensa
+toolchain:
+  - xtools
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/xtensa/qemu_xtensa/qemu_xtensa_dc233c_defconfig

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_BOARD_QEMU_XTENSA_DC233C=y
+CONFIG_CONSOLE=y
+CONFIG_SOC_XTENSA_DC233C=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
+CONFIG_STACK_SENTINEL=y
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+CONFIG_SIMULATOR_XTENSA=y
+CONFIG_QEMU_ICOUNT_SHIFT=6

dts/xtensa/dc233c.dtsi

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx3";
+			reg = <0>;
+		};
+	};
+
+	/*
+	 * Although RAM is of size 128MB (0x08000000), limit this to 16MB so
+	 * fewer L2 page table entries are needed when MMU is enabled.
+	 */
+	sram0: memory@00000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x00000000 0x01000000>;
+	};
+
+	/*
+	 * Although ROM is of size 32MB (0x02000000), limit this to 8KB so
+	 * fewer L2 page table entries are needed when MMU is enabled.
+	 */
+	rom0: memory@fe000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xfe000000 0x00002000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+	};
+};

soc/xtensa/dc233c/CMakeLists.txt

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU mmu.c)

soc/xtensa/dc233c/Kconfig.defconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 Cadence Design Systems, Inc.
+# Copyright (c) 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_XTENSA_DC233C
+
+config SOC
+	default "dc233c"
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "dc233c"
+
+config XTENSA_MMU_NUM_L2_TABLES
+	int
+	default 48 if XTENSA_MMU
+
+# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB.
+# This is to allow VECBASE to be mapped permanently
+# via TLB way 4 (which covers 1MB).
+config SRAM_OFFSET
+	hex
+	default 0x100000
+
+config KERNEL_VM_OFFSET
+	hex
+	default 0x100000
+
+endif

soc/xtensa/dc233c/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2017, 2023 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XTENSA_DC233C
+	bool "Xtensa dc233c core"
+	select XTENSA
+	select XTENSA_HAL
+	select CPU_HAS_MMU
+	imply XTENSA_MMU
+	select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU