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boards: arm: mimxrt595_evk: remove RK055HDMIPI4M display definition
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Remove display definition from RT595 EVK, as this is now supported by
the shield. Add gpio nexus for the FFC connector on this EVK.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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@danieldegrasse
danieldegrasse committed Mar 6, 2023
1 parent 46a1388 commit 2795083
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Showing 3 changed files with 27 additions and 102 deletions.
40 changes: 0 additions & 40 deletions boards/arm/mimxrt595_evk/Kconfig.defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -29,44 +29,4 @@ config HEAP_MEM_POOL_SIZE

endif # DMA_MCUX_LPC

if DISPLAY

# Enable MIPI display driver

config MIPI_DSI
default y

# Use external framebuffer memory for the LCDIF framebuffer
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
default y
# Use FlexSPI2 base address for framebuffer (pSRAM is present on this bus)
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
default 0x38000000
# M33 core and LCDIF both access FlexSPI2 through the same cache,
# so coherency does not need to be managed.
config MCUX_DCNANO_LCDIF_MAINTAIN_CACHE
depends on !MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM

endif # DISPLAY

config KSCAN
default y if LVGL

if LVGL

config LV_Z_POINTER_KSCAN
default y

config LV_Z_VDB_SIZE
default 16

config LV_Z_DPI
default 128

choice LV_COLOR_DEPTH
default LV_COLOR_DEPTH_16
endchoice

endif # LVGL

endif # BOARD_MIMXRT595_EVK
4 changes: 2 additions & 2 deletions boards/arm/mimxrt595_evk/doc/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,8 @@ already supported, which can also be re-used on this mimxrt595_evk board:
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access (works with eMMC & SD) |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with RM68200|
| | | based MIPI display |
| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with |
| | | rk055hdmipi4m display shield |
| | | (`RK055HDMIPI4M`_) |
+-----------+------------+-------------------------------------+

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85 changes: 25 additions & 60 deletions boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,28 @@
<21 0 &gpio4 21 0>; /* D15 */
};

/*
* This node describes the GPIO pins of the MIPI FPC interface,
* J44 on the EVK. This interface is standard to several
* NXP EVKs, and is used with several MIPI displays
* (available as zephyr shields)
*/
mipi_connector: mipi-connector {
compatible = "gpio-nexus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */
<21 0 &gpio3 21 0>, /* Pin 21, RESET */
<22 0 &gpio3 18 0>, /* Pin 22, LPTE */
<26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */
<27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */
<28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */
<29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */
<32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */
<34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */
};

power-states {
/* This is the setting Sleep Mode */
idle: idle {
Expand Down Expand Up @@ -154,54 +176,6 @@
status = "okay";
};

&lcdif {
status = "okay";
width = <720>;
height = <1280>;
polarity = <(LCDIF_DE_ACTIVE_HIGH | LCDIF_PXCLOCK_RISING)>;
hsync = <8>;
hfp = <32>;
hbp = <32>;
vsync = <2>;
vfp = <16>;
vbp = <14>;
backlight-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
data-bus-width = "24-bit";
pixel-format = <LCDIF_PIXEL_FORMAT_BGR_565>;
/*
* Pixel clock is given by the following formula:
* (height + vsync + vfp + vbp) *
* (width + hsync + hfp + hbp) * frame rate
*/
pixel-clock = <62346240>;
};

&mipi_dsi {
status = "okay";
nxp,lcdif = <&lcdif>;
dpi-color-coding = "24-bit";
dpi-pixel-packet = "24-bit";
dpi-video-mode = "burst";
dpi-bllp-mode = "low-power";
autoinsert-eotp;
/*
* PHY clock is given by the following formula:
* (pixel clock * bits per pixel) / MIPI data lanes
*/
phy-clock = <748154880>;

rm68200@0 {
status = "okay";
compatible = "raydium,rm68200";
reg = <0x0>;
reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
data-lanes = <2>;
width = <720>;
height = <1280>;
pixel-format = <MIPI_DSI_PIXFMT_RGB565>;
};
};

&flexcomm0 {
compatible = "nxp,lpc-usart";
status = "okay";
Expand All @@ -210,6 +184,7 @@
pinctrl-names = "default";
};


arduino_i2c: &flexcomm4 {
compatible = "nxp,lpc-i2c";
status = "okay";
Expand All @@ -225,15 +200,10 @@ arduino_i2c: &flexcomm4 {
int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};

touch_controller: gt911@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
};
};

mipi_i2c: &arduino_i2c {};

hs_spi1: &hs_lspi1 {
compatible = "nxp,lpc-spi";
pinctrl-0 = <&pinmux_flexcomm16_spi>;
Expand Down Expand Up @@ -447,10 +417,6 @@ zephyr_udc0: &usbhs {
};
};

/*
* Configure FlexSPI2 to use 1KB of AHB RX buffer for GPU/Display master.
* This will improve performance when using external pSRAM with the LCDIF.
*/
&flexspi2 {
status = "okay";
pinctrl-0 = <&pinmux_flexspi2>;
Expand All @@ -460,7 +426,6 @@ zephyr_udc0: &usbhs {
ahb-bufferable;
ahb-cacheable;
ahb-read-addr-opt;
rx-buffer-config = <1 7 11 1024>;
aps6408l: aps6408l@0 {
compatible = "nxp,imx-flexspi-aps6408l";
/* APS6408L is 8MB, 64MBit pSRAM */
Expand Down

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