tests: drivers: build_all: Build Altera FPGA driver

Altera FPGA driver should be built on a regular basis to ensure that there are no regressions Signed-off-by: Hardeep Sharma <hardeep.sharma@intel.com>
zephyrproject-rtos · Apr 23, 2024 · 31dc1e8 · 31dc1e8
1 parent 6b4f612
commit 31dc1e8
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diff --git a/tests/drivers/build_all/fpga/app.overlay b/tests/drivers/build_all/fpga/app.overlay
@@ -44,3 +44,12 @@
  * here to keep the bus specific dtsi files (i2c.dtsi, spi.dtsi, etc..)
  * pristine
  */
+
+&sip_smc {
+		status = "okay";
+		zephyr,num-clients = <2>;
+	};
+
+&fpga0 {
+	status = "okay";
+};
diff --git a/tests/drivers/build_all/fpga/boards/intel_socfpga_agilex5_socdk.conf b/tests/drivers/build_all/fpga/boards/intel_socfpga_agilex5_socdk.conf
@@ -0,0 +1,9 @@
+# Copyright (c) 2024, Intel Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# FPGA Bridge
+CONFIG_ALTERA_AGILEX_BRIDGE_FPGA=y
+CONFIG_ARM_SIP_SVC_DRIVER=y
+CONFIG_ARM_SIP_SVC_SUBSYS=y
+CONFIG_ARM_SIP_SVC_SUBSYS_SINGLY_OPEN=y
+CONFIG_HEAP_MEM_POOL_SIZE=16384
diff --git a/tests/drivers/build_all/fpga/boards/intel_socfpga_agilex_socdk.conf b/tests/drivers/build_all/fpga/boards/intel_socfpga_agilex_socdk.conf
@@ -0,0 +1,9 @@
+# Copyright (c) 2024, Intel Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+# FPGA Bridge
+CONFIG_ALTERA_AGILEX_BRIDGE_FPGA=y
+CONFIG_ARM_SIP_SVC_DRIVER=y
+CONFIG_ARM_SIP_SVC_SUBSYS=y
+CONFIG_ARM_SIP_SVC_SUBSYS_SINGLY_OPEN=y
+CONFIG_HEAP_MEM_POOL_SIZE=16384