arm: Add Broadcom Valkyrie SoC support

Add initial support for Broadcom Valkyrie SoC as part of Zephyr. Signed-off-by: Scott Branden <scott.branden@broadcom.com>
zephyrproject-rtos · Jan 30, 2020 · 54ce0b2 · 54ce0b2
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diff --git a/CODEOWNERS b/CODEOWNERS
@@ -26,6 +26,7 @@
 /soc/arm/arm/mps2/                        @fvincenzo
 /soc/arm/atmel_sam/sam3x/                 @ioannisg
 /soc/arm/atmel_sam/sam4s/                 @fallrisk
+/soc/arm/bcm*/                            @sbranden
 /soc/arm/nxp*/                            @MaureenHelm
 /soc/arm/nordic_nrf/                      @ioannisg
 /soc/arm/st_stm32/                        @erwango
@@ -205,6 +206,7 @@
 /dts/arc/                                 @vonhust @ruuddw @iriszzw
 /dts/arm/atmel/samr21.dtsi                @benpicco
 /dts/arm/atmel/sam*5*.dtsi                @benpicco
+/dts/arm/broadcom/                        @sbranden
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon
 /dts/arm/ti/cc26?2*                       @bwitherspoon

diff --git a/dts/arm/broadcom/valkyrie-irq.h b/dts/arm/broadcom/valkyrie-irq.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright 2018 Broadcom.
+ */
+
+#ifndef VALKYRIE_IRQ_H
+#define VALKYRIE_IRQ_H
+
+#define SPI_RESERVED7_7			239
+#define SPI_RESERVED7_6			238
+#define SPI_RESERVED7_5			237
+#define SPI_RESERVED7_4			236
+#define SPI_RESERVED7_3			235
+#define SPI_RESERVED7_2			234
+#define SPI_RESERVED7_1			233
+#define SPI_RESERVED7_0			232
+#define SPI_RESERVED6_13		231
+#define SPI_RESERVED6_12		230
+#define SPI_RESERVED6_11		229
+#define SPI_RESERVED6_10		228
+#define SPI_RESERVED6_9			227
+#define SPI_RESERVED6_8			226
+#define SPI_RESERVED6_7			225
+#define SPI_RESERVED6_6			224
+#define SPI_RESERVED6_5			223
+#define SPI_RESERVED6_4			222
+#define SPI_RESERVED6_3			221
+#define SPI_RESERVED6_2			220
+#define SPI_RESERVED6_1			219
+#define SPI_RESERVED6_0			218
+#define SMU_DMU_AUTH_ERR		217
+#define SMU_DMU_PAR_ERR			216
+#define SMU_INTR			215
+#define IRQ_SMAU_S0_PINS_BUS		214
+#define IRQ_ROM_S0_PINS_BUS		213
+#define IRQ_QSPI_S0_PINS_BUS		212
+#define IRQ_NAND_S0_PINS_BUS		211
+#define DMA_ARB_ERR_INTR		210
+#define IRQ_CORESIGHT_M0_PINS_BUS	209
+#define IRQ_APB_LS3_PINS_BUS		208
+#define IRQ_APB_LS2_PINS_BUS		207
+#define IRQ_APB_LS1_PINS_BUS		206
+#define QSPI_INTERRUPT_O		205
+#define NAND_INTERRUPT_O		204
+#define LS_GPIO_INTR			203
+#define RNG_INTR			202
+#define WDOG_INTR			201
+#define UART3_INTR			200
+#define UART2_INTR			199
+#define UART1_INTR			198
+#define UART0_INTR			197
+#define TIM3_INTR			196
+#define TIM2_INTR			195
+#define TIM1_INTR			194
+#define TIM0_INTR			193
+#define SPI2_INTR			192
+#define SPI1_INTR			191
+#define SPI0_INTR			190
+#define SMBUS1_INTR			189
+#define SMBUS0_INTR			188
+#define MIIM_PAUSE_SCAN_STATUS_CHANGE	187
+#define MIIM_OP_DONE			186
+#define MIIM_LINK_SCAN_STATUS_CHANGE	185
+#define ETIMER_1_TM_INTR3		184
+#define ETIMER_1_TM_INTR2		183
+#define ETIMER_1_TM_INTR1		182
+#define ETIMER_1_TM_INTR0		181
+#define ETIMER_0_TM_INTR3		180
+#define ETIMER_0_TM_INTR2		179
+#define ETIMER_0_TM_INTR1		178
+#define ETIMER_0_TM_INTR0		177
+#define DMAC_IRQ_ABORT			176
+#define DMAC_IRQ7			175
+#define DMAC_IRQ6			174
+#define DMAC_IRQ5			173
+#define DMAC_IRQ4			172
+#define DMAC_IRQ3			171
+#define DMAC_IRQ2			170
+#define DMAC_IRQ1			169
+#define DMAC_IRQ0			168
+#define SPI_RESERVED5_7			167
+#define SPI_RESERVED5_6			166
+#define SPI_RESERVED5_5			165
+#define SPI_RESERVED5_4			164
+#define SPI_RESERVED5_3			163
+#define SPI_RESERVED5_2			162
+#define SPI_RESERVED5_1			161
+#define SPI_RESERVED5_0			160
+#define DDR1_INTERRUPT3			159
+#define DDR1_INTERRUPT2			158
+#define DDR1_INTERRUPT1			157
+#define DDR1_INTERRUPT0			156
+#define DDR0_INTERRUPT3			155
+#define DDR0_INTERRUPT2			154
+#define DDR0_INTERRUPT1			153
+#define DDR0_INTERRUPT0			152
+#define DDR1_TZC_INTERRUPT		151
+#define DDR0_TZC_INTERRUPT		150
+#define SPI_RESERVED4_0			149
+#define PMON_INTERRUPT			148
+#define SRAM_TZC_INTERRUPT		147
+#define SCR_SRAM_INTERRUPT		146
+#define IRQ_GIC_S0_PINS_BUS		145
+#define IRQ_CRMU_S0_PINS_BUS		144
+#define IRQ_CRMU_M0_PINS_BUS		143
+#define IRQ_APB_SCR2_PINS_BUS		142
+#define IRQ_APB_SCR1_PINS_BUS		141
+#define SPI_RESERVED3_3			140
+#define SPI_RESERVED3_2			139
+#define SPI_RESERVED3_1			138
+#define SPI_RESERVED3_0			137
+#define VID_MSTR_RESP_ERR_INTR		136
+#define PCIE_RM_ERR_INTR		135
+#define PCIE_ARB_ERR_INTR		134
+#define PCIE_GLOBAL_ERR_INTR		133
+#define IRQ_PCIE_NIC_S_PINS_BUS		132
+#define IRQ_PCIE_S1_PINS_BUS		131
+#define IRQ_PCIE_S0_PINS_BUS		130
+#define PAXB1_MSIX_INTR15		129
+#define PAXB1_MSIX_INTR14		128
+#define PAXB1_MSIX_INTR13		127
+#define PAXB1_MSIX_INTR12		126
+#define PAXB1_MSIX_INTR11		125
+#define PAXB1_MSIX_INTR10		124
+#define PAXB1_MSIX_INTR9		123
+#define PAXB1_MSIX_INTR8		122
+#define PAXB1_MSIX_INTR7		121
+#define PAXB1_MSIX_INTR6		120
+#define PAXB1_MSIX_INTR5		119
+#define PAXB1_MSIX_INTR4		118
+#define PAXB1_MSIX_INTR3		117
+#define PAXB1_MSIX_INTR2		116
+#define PAXB1_MSIX_INTR1		115
+#define PAXB1_MSIX_INTR0		114
+#define PAXB1_GIC_MEM_ERR_INTR		113
+#define PAXB1_GIC_INTR5			112
+#define PAXB1_GIC_INTR4			111
+#define PAXB1_GIC_INTR3			110
+#define PAXB1_GIC_INTR2			109
+#define PAXB1_GIC_INTR1			108
+#define PAXB1_GIC_INTR0			107
+#define PAXB1_AXI_IBUF_INTR		106
+#define PAXB0_MSIX_INTR15		105
+#define PAXB0_MSIX_INTR14		104
+#define PAXB0_MSIX_INTR13		103
+#define PAXB0_MSIX_INTR12		102
+#define PAXB0_MSIX_INTR11		101
+#define PAXB0_MSIX_INTR10		100
+#define PAXB0_MSIX_INTR9		99
+#define PAXB0_MSIX_INTR8		98
+#define PAXB0_MSIX_INTR7		97
+#define PAXB0_MSIX_INTR6		96
+#define PAXB0_MSIX_INTR5		95
+#define PAXB0_MSIX_INTR4		94
+#define PAXB0_MSIX_INTR3		93
+#define PAXB0_MSIX_INTR2		92
+#define PAXB0_MSIX_INTR1		91
+#define PAXB0_MSIX_INTR0		90
+#define PAXB0_GIC_MEM_ERR_INTR		89
+#define PAXB0_GIC_INTR5			88
+#define PAXB0_GIC_INTR4			87
+#define PAXB0_GIC_INTR3			86
+#define PAXB0_GIC_INTR2			85
+#define PAXB0_GIC_INTR1			84
+#define PAXB0_GIC_INTR0			83
+#define PAXB0_AXI_IBUF_INTR		82
+#define IHOST_NINTERRIRQ		81
+#define IHOST_NEXTERRIRQ		80
+#define IHOST_CRM_INTERRUPT		79
+#define DEC0_IRQ			78
+#define DEC1_IRQ			77
+#define ENC0_IRQ			76
+#define ENC1_IRQ			75
+#define ENC2_IRQ			74
+#define SCL0_IRQ			73
+#define SCL1_IRQ			72
+#define SSIM0_AFBC_IRQ_SURFACES_DONE	71
+#define SSIM0_AFBC_IRQ_SECURE_ID_ERR	70
+#define SSIM0_AFBC_IRQ_DETLING_ERR	69
+#define SSIM0_AFBC_IRQ_DECODE_ERR	68
+#define SSIM0_AFBC_IRQ_CONFIG_SWAP	67
+#define SSIM0_AFBC_IRQ_AXI_ERR		66
+#define SSIM0_AFBC_IRQ			65
+#define SSIM0_IRQ			64
+#define SSIM1_AFBC_IRQ_SURFACES_DONE	63
+#define SSIM1_AFBC_IRQ_SECURE_ID_ERR	62
+#define SSIM1_AFBC_IRQ_DETLING_ERR	61
+#define SSIM1_AFBC_IRQ_DECODE_ERR	60
+#define SSIM1_AFBC_IRQ_CONFIG_SWAP	59
+#define SSIM1_AFBC_IRQ_AXI_ERR		58
+#define SSIM1_AFBC_IRQ			57
+#define SSIM1_IRQ			56
+#define SSIM2_AFBC_IRQ_SURFACES_DONE	55
+#define SSIM2_AFBC_IRQ_SECURE_ID_ERR	54
+#define SSIM2_AFBC_IRQ_DETLING_ERR	53
+#define SSIM2_AFBC_IRQ_DECODE_ERR	52
+#define SSIM2_AFBC_IRQ_CONFIG_SWAP	51
+#define SSIM2_AFBC_IRQ_AXI_ERR		50
+#define SSIM2_AFBC_IRQ			49
+#define SSIM2_IRQ			48
+#define PCIE1_INB_PERSTB_EVENT		47
+#define PCIE0_INB_PERSTB_EVENT		46
+#define PCIE1_PERSTB_EVENT		45
+#define PCIE0_PERSTB_EVENT		44
+#define MCU_NS_MAILBOX3_EVENT		43
+#define MCU_NS_MAILBOX2_EVENT		42
+#define MCU_NS_MAILBOX1_EVENT		41
+#define MCU_NS_MAILBOX0_EVENT		40
+#define RESERVED_39			39
+#define RESERVED_38			38
+#define RESERVED_37			37
+#define RESERVED_36			36
+#define RESERVED_35			35
+#define MCU_COMB_IDM_INTR		34
+#define MCU_TIMER2_INTR			33
+#define MCU_TIMER1_INTR			32
+#define MCU_MAILBOX_EVENT		31
+#define MCU_IPROC_STANDBYWFI_EVENT	30
+#define MCU_IPROC_STANDBYWFE_EVENT	29
+#define RESERVED_28			28
+#define RESERVED_27			27
+#define RESERVED_26			26
+#define MCU_MAILBOX1_EVENT		25
+#define RESERVED_24			24
+#define RESERVED_23			23
+#define RESERVED_22			22
+#define RESERVED_21			21
+#define RESERVED_20			20
+#define RESERVED_19			19
+#define GIC_ECC_ERR_INITR		18
+#define GIC_AXI_ERR_INITR		17
+#define AVS_TEMP_RESET_INTR		16
+#define AVS_MONITOR_INTR		15
+#define MCU_SECURITY_INTR		14
+#define RESERVED_13			13
+#define RESERVED_12			12
+#define MCU_RESET_LOG_INTR		11
+#define MCU_POWER_LOG_INTR		10
+#define MCU_ERROR_LOG_INTR		9
+#define MCU_WDOG_INTR			8
+#define MCU_TIMER_INTR			7
+#define MCU_SMBUS_INTR			6
+#define RESERVED_5			5
+#define RESERVED_4			4
+#define CHIPCOMMONG_WDOG_RESET		3
+#define MCU_AON_GPIO_INTR		2
+#define MCU_AON_UART_INTR		1
+#define RESERVED_0			0
+#endif
diff --git a/dts/arm/broadcom/valkyrie.dtsi b/dts/arm/broadcom/valkyrie.dtsi
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright 2018 Broadcom.
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <broadcom/valkyrie-irq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <16>;
+			};
+		};
+	};
+
+	soc {
+		sram0: memory@400000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x00400000 0x30000>;
+		};
+
+		uart0: uart@40020000 {
+			compatible = "ns16550";
+			reg = <0x40020000 0x400>;
+			clock-frequency = <25000000>;
+			interrupts = <MCU_AON_UART_INTR 3>;
+			label = "UART_0";
+			status = "disabled";
+		};
+
+		uart1: uart@48100000 {
+			compatible = "ns16550";
+			reg = <0x48100000 0x400>;
+			clock-frequency = <100000000>;
+			interrupts = <UART0_INTR 3>;
+			label = "UART_1";
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/soc/arm/bcm_vk/CMakeLists.txt b/soc/arm/bcm_vk/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
diff --git a/soc/arm/bcm_vk/Kconfig b/soc/arm/bcm_vk/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2020 Broadcom.
+#
+
+config SOC_FAMILY_BCMVK
+	bool
+
+if SOC_FAMILY_BCMVK
+config SOC_FAMILY
+	string
+	default "bcm_vk"
+
+source "soc/arm/bcm_vk/*/Kconfig.soc"
+
+endif
diff --git a/soc/arm/bcm_vk/Kconfig.defconfig b/soc/arm/bcm_vk/Kconfig.defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2020 Broadcom.
+#
+
+source "soc/arm/bcm_vk/*/Kconfig.defconfig.series"
diff --git a/soc/arm/bcm_vk/Kconfig.soc b/soc/arm/bcm_vk/Kconfig.soc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2020 Broadcom.
+#
+
+source "soc/arm/bcm_vk/*/Kconfig.series"
diff --git a/soc/arm/bcm_vk/valkyrie/CMakeLists.txt b/soc/arm/bcm_vk/valkyrie/CMakeLists.txt
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(
+	soc.c
+)
diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2020 Broadcom.
+#
+
+if SOC_SERIES_VALKYRIE
+
+config SOC_SERIES
+	default "valkyrie"
+
+config NUM_IRQS
+	int
+	default 240
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 500000000
+
+source "soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie*"
+
+endif # SOC_SERIES_VALKYRIE