codeowners: Add code owner for INTEL FPGA Nios V/g

Add code owner for INTEL FPGA Nios V/g dts, SoC and board.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>

CODEOWNERS

@@ -179,7 +179,7 @@
 /boards/riscv/adp_xc7k_ae350/             @cwshu @kevinwang821020 @jimmyzhe
 /boards/riscv/longan_nano/                @soburi
 /boards/riscv/neorv32/                    @henrikbrixandersen
-/boards/riscv/niosv_m/                    @sweeaun
+/boards/riscv/niosv*/                     @sweeaun
 /boards/shields/                          @erwango
 /boards/shields/atmel_rf2xx/              @nandojve
 /boards/shields/esp_8266/                 @nandojve
@@ -531,7 +531,7 @@
 /dts/riscv/riscv32-litex-vexriscv.dtsi    @mateusz-holenko @kgugala @pgielda
 /dts/riscv/starfive/                      @rajnesh-kanwal
 /dts/riscv/andes/andes_v5*                @cwshu @kevinwang821020 @jimmyzhe
-/dts/riscv/niosv/niosv-m.dtsi             @sweeaun
+/dts/riscv/niosv/                         @sweeaun
 /dts/arm/armv*m.dtsi                      @galak @ioannisg
 /dts/arm/armv7-a.dtsi                     @ibirnbaum
 /dts/arm/armv7-r.dtsi                     @bbolen @stephanosio