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ext: hal: nxp: mcux: add device files for RT1015

Add mcux 2.5.0 drivers and device header files for mimxrt1015. Update
several drivers that were already imported for other SoCs but also apply
to mimxrt1015.

Origins: NXP MCUxpresso SDK 2.5.0
URL: mcuxpresso.nxp.com
Maintained-by: External

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
  • Loading branch information...
jhqian authored and MaureenHelm committed Mar 4, 2019
1 parent 8a4dbb5 commit 55a63cadc1013ab8070bb0afdb2602770cbf3707
Showing with 171,496 additions and 3,341 deletions.
  1. +1 −0 ext/hal/nxp/mcux/README
  2. +1 −0 ext/hal/nxp/mcux/boards/CMakeLists.txt
  3. +10 −0 ext/hal/nxp/mcux/boards/evkmimxrt1015/CMakeLists.txt
  4. +48 −0 ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.c
  5. +268 −0 ext/hal/nxp/mcux/boards/evkmimxrt1015/evkmimxrt1015_flexspi_nor_config.h
  6. +32,299 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.h
  7. +130,321 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015.xml
  8. +504 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/MIMXRT1015_features.h
  9. +907 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.c
  10. +1,286 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_clock.h
  11. +35 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_device_registers.h
  12. +565 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/fsl_iomuxc.h
  13. +217 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.c
  14. +118 −0 ext/hal/nxp/mcux/devices/MIMXRT1015/system_MIMXRT1015.h
  15. +12 −12 ext/hal/nxp/mcux/drivers/imx/fsl_adc.c
  16. +16 −16 ext/hal/nxp/mcux/drivers/imx/fsl_adc.h
  17. +64 −64 ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.c
  18. +100 −100 ext/hal/nxp/mcux/drivers/imx/fsl_adc_etc.h
  19. +4 −4 ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.c
  20. +28 −23 ext/hal/nxp/mcux/drivers/imx/fsl_aipstz.h
  21. +5 −6 ext/hal/nxp/mcux/drivers/imx/fsl_aoi.h
  22. +12 −12 ext/hal/nxp/mcux/drivers/imx/fsl_bee.c
  23. +12 −14 ext/hal/nxp/mcux/drivers/imx/fsl_bee.h
  24. +13 −13 ext/hal/nxp/mcux/drivers/imx/fsl_cache.c
  25. +48 −49 ext/hal/nxp/mcux/drivers/imx/fsl_cache.h
  26. +9 −9 ext/hal/nxp/mcux/drivers/imx/fsl_common.c
  27. +26 −24 ext/hal/nxp/mcux/drivers/imx/fsl_common.h
  28. +140 −143 ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.c
  29. +164 −164 ext/hal/nxp/mcux/drivers/imx/fsl_dcdc.h
  30. +48 −48 ext/hal/nxp/mcux/drivers/imx/fsl_dcp.c
  31. +30 −30 ext/hal/nxp/mcux/drivers/imx/fsl_dcp.h
  32. +11 −12 ext/hal/nxp/mcux/drivers/imx/fsl_dmamux.h
  33. +228 −175 ext/hal/nxp/mcux/drivers/imx/fsl_edma.c
  34. +47 −39 ext/hal/nxp/mcux/drivers/imx/fsl_edma.h
  35. +15 −15 ext/hal/nxp/mcux/drivers/imx/fsl_enc.c
  36. +21 −21 ext/hal/nxp/mcux/drivers/imx/fsl_enc.h
  37. +9 −9 ext/hal/nxp/mcux/drivers/imx/fsl_ewm.c
  38. +8 −9 ext/hal/nxp/mcux/drivers/imx/fsl_ewm.h
  39. +12 −12 ext/hal/nxp/mcux/drivers/imx/fsl_flexio.c
  40. +61 −61 ext/hal/nxp/mcux/drivers/imx/fsl_flexio.h
  41. +82 −77 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.c
  42. +12 −12 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2c_master.h
  43. +115 −115 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.c
  44. +22 −22 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s.h
  45. +22 −22 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.c
  46. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_i2s_edma.h
  47. +123 −123 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.c
  48. +17 −17 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi.h
  49. +26 −26 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.c
  50. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_spi_edma.h
  51. +73 −73 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.c
  52. +8 −8 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart.h
  53. +5 −5 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.c
  54. +3 −3 ext/hal/nxp/mcux/drivers/imx/fsl_flexio_uart_edma.h
  55. +3 −3 ext/hal/nxp/mcux/drivers/imx/fsl_flexram.c
  56. +15 −15 ext/hal/nxp/mcux/drivers/imx/fsl_flexram.h
  57. +60 −60 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.c
  58. +56 −56 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi.h
  59. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.c
  60. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h
  61. +3 −3 ext/hal/nxp/mcux/drivers/imx/fsl_gpc.c
  62. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_gpc.h
  63. +7 −7 ext/hal/nxp/mcux/drivers/imx/fsl_gpio.c
  64. +15 −15 ext/hal/nxp/mcux/drivers/imx/fsl_gpio.h
  65. +5 −5 ext/hal/nxp/mcux/drivers/imx/fsl_gpt.c
  66. +16 −16 ext/hal/nxp/mcux/drivers/imx/fsl_gpt.h
  67. +2 −2 ext/hal/nxp/mcux/drivers/imx/fsl_kpp.c
  68. +11 −9 ext/hal/nxp/mcux/drivers/imx/fsl_kpp.h
  69. +61 −61 ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.c
  70. +51 −52 ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c.h
  71. +31 −31 ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.c
  72. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_lpi2c_edma.h
  73. +145 −146 ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.c
  74. +83 −85 ext/hal/nxp/mcux/drivers/imx/fsl_lpspi.h
  75. +96 −94 ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.c
  76. +4 −4 ext/hal/nxp/mcux/drivers/imx/fsl_lpspi_edma.h
  77. +255 −208 ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.c
  78. +46 −47 ext/hal/nxp/mcux/drivers/imx/fsl_lpuart.h
  79. +68 −59 ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.c
  80. +5 −5 ext/hal/nxp/mcux/drivers/imx/fsl_lpuart_edma.h
  81. +3 −3 ext/hal/nxp/mcux/drivers/imx/fsl_pit.c
  82. +3 −3 ext/hal/nxp/mcux/drivers/imx/fsl_pit.h
  83. +11 −11 ext/hal/nxp/mcux/drivers/imx/fsl_pmu.h
  84. +7 −7 ext/hal/nxp/mcux/drivers/imx/fsl_pwm.c
  85. +24 −25 ext/hal/nxp/mcux/drivers/imx/fsl_pwm.h
  86. +2 −2 ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.c
  87. +12 −9 ext/hal/nxp/mcux/drivers/imx/fsl_qtmr.h
  88. +14 −14 ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.c
  89. +43 −6 ext/hal/nxp/mcux/drivers/imx/fsl_rtwdog.h
  90. +930 −77 ext/hal/nxp/mcux/drivers/imx/fsl_sai.c
  91. +537 −80 ext/hal/nxp/mcux/drivers/imx/fsl_sai.h
  92. +101 −28 ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.c
  93. +24 −4 ext/hal/nxp/mcux/drivers/imx/fsl_sai_edma.h
  94. +10 −10 ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.c
  95. +24 −24 ext/hal/nxp/mcux/drivers/imx/fsl_snvs_hp.h
  96. +10 −10 ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.c
  97. +15 −16 ext/hal/nxp/mcux/drivers/imx/fsl_snvs_lp.h
  98. +38 −38 ext/hal/nxp/mcux/drivers/imx/fsl_spdif.c
  99. +37 −37 ext/hal/nxp/mcux/drivers/imx/fsl_spdif.h
  100. +28 −28 ext/hal/nxp/mcux/drivers/imx/fsl_spdif_edma.c
  101. +22 −18 ext/hal/nxp/mcux/drivers/imx/fsl_src.h
  102. +4 −4 ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.c
  103. +2 −2 ext/hal/nxp/mcux/drivers/imx/fsl_tempmon.h
  104. +236 −180 ext/hal/nxp/mcux/drivers/imx/fsl_trng.c
  105. +29 −35 ext/hal/nxp/mcux/drivers/imx/fsl_trng.h
  106. +12 −12 ext/hal/nxp/mcux/drivers/imx/fsl_wdog.c
  107. +5 −5 ext/hal/nxp/mcux/drivers/imx/fsl_wdog.h
  108. +29 −68 ext/hal/nxp/mcux/drivers/imx/fsl_xbara.c
  109. +8 −8 ext/hal/nxp/mcux/drivers/imx/fsl_xbara.h
  110. +1 −1 ext/hal/nxp/mcux/drivers/imx/fsl_xbarb.h
@@ -15,6 +15,7 @@ Status:

SoC Version (Release Date) Tag
----------------------------------------------------------------------------
MIMXRT1015 SDK 2.5.0 (2019-03-11) REL_2.5.0_RT1015_RFP
LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
@@ -4,6 +4,7 @@
# SPDX-License-Identifier: Apache-2.0
#

add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1015_EVK evkmimxrt1015)
add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1020_EVK evkmimxrt1020)
add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1050_EVK evkbimxrt1050)
add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1050_EVK_QSPI evkbimxrt1050)
@@ -0,0 +1,10 @@
#
# Copyright (c) 2018, NXP
#
# SPDX-License-Identifier: Apache-2.0
#

zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1)
zephyr_compile_definitions_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA XIP_BOOT_HEADER_DCD_ENABLE=1)

zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR evkmimxrt1015_flexspi_nor_config.c)
@@ -0,0 +1,48 @@
/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#include "evkmimxrt1015_flexspi_nor_config.h"

/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif

/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif

const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */
@@ -0,0 +1,268 @@
/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__

#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"

/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/

/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)

/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1

/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4

#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9

#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0

#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3

#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))

//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;

//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};

//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;

//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};

//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};

//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};

//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;

//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};

//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;

/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7

#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk

/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */

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