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tests: drivers: uart_async: stm32: add test cases with DCache enabled
Add test cases/configs for async DMA uart with DCache on STM32F7/H7 boards Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
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tests/drivers/uart/uart_async_api/boards/nucleo_f746zg_nocachemem.overlay
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/* | ||
* Copyright (c) 2024 STMicroelectronics | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> | ||
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/ { | ||
/* The async_api.nocache_mem_dt test case expects a non-cachable RAM region */ | ||
sram_nocache: memory@2004c000 { | ||
compatible = "zephyr,memory-region", "mmio-sram"; | ||
reg = <0x2004c000 DT_SIZE_K(16)>; | ||
zephyr,memory-region = "RAM_NOCACHE"; | ||
zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>; | ||
}; | ||
}; |
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tests/drivers/uart/uart_async_api/boards/nucleo_h723zg.overlay
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tests/drivers/uart/uart_async_api/boards/nucleo_h723zg_nocachemem.overlay
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/* | ||
* Copyright (c) 2024 STMicroelectronics | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> | ||
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&sram1 { | ||
zephyr,memory-attr = <DT_MEM_ARM_MPU_RAM_NOCACHE>; | ||
zephyr,memory-region = "RAM_NOCACHE"; | ||
}; |
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CONFIG_DCACHE=y | ||
CONFIG_DT_DEFINED_NOCACHE=y | ||
CONFIG_DT_DEFINED_NOCACHE_NAME="RAM_NOCACHE" | ||
CONFIG_USERSPACE=n |
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