boards: Add support for the NXP MIMXRT595 DSP core

Add board and soc files for the audio DSP in NXP MIMXRT595.

Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>

boards/arm/mimxrt595_evk/doc/index.rst

@@ -174,6 +174,30 @@ Serial Port
 The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is
 configured as USART for the console and the remaining are not used.
 
+Fusion F1 DSP Core
+==================
+
+You can build a Zephyr application for the RT595 DSP core using nxp_adsp_rt595
+board. Xtensa toolchain and RT595 DSP build configuration are required for
+this. For instructions on how to download the toolchain and debug DSP firmware,
+please refer to this document: `Getting Started with Xplorer for EVK-MIMXRT595`_
+
+The following environment variables must be set prior to building RT595 DSP
+application:
+
+.. code-block:: shell
+
+   export ZEPHYR_TOOLCHAIN_VARIANT=xt-clang
+   export XTENSA_TOOLCHAIN_PATH=<path to dir where XtensaTools is located>
+   export XTENSA_CORE=nxp_rt500_RI2020_5_newlib
+
+Once the environment variables are set, Zephyr application for the DSP core
+can be built with:
+
+.. code-block:: shell
+
+   $ west build -b nxp_adsp_rt595 samples/hello_world
+
 Programming and Debugging
 *************************
 
@@ -313,3 +337,6 @@ steps:
 
 .. _i.MX RT595 Reference Manual:
    https://www.nxp.com/webapp/Download?colCode=IMXRT500RM
+
+.. _Getting Started with Xplorer for EVK-MIMXRT595:
+   https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf

boards/xtensa/nxp_adsp_rt595/Kconfig

@@ -0,0 +1,42 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
+DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
+DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text)
+
+if BOARD_NXP_ADSP_RT595
+
+config RT595_ADSP_STACK_SIZE
+	hex "Boot time stack size"
+	default 0x1000
+	help
+	  Stack space is reserved at the end of the RT595_ADSP_DATA_MEM
+	  region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE
+
+config RT595_ADSP_RESET_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM))
+
+config RT595_ADSP_RESET_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM))
+
+config RT595_ADSP_DATA_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM))
+
+config RT595_ADSP_DATA_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM))
+
+config RT595_ADSP_TEXT_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM))
+
+config RT595_ADSP_TEXT_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM))
+
+endif # BOARD_NXP_ADSP_RT595
+

boards/xtensa/nxp_adsp_rt595/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NXP_ADSP_RT595
+	bool "NXP ADSP RT595"
+	depends on SOC_SERIES_NXP_RT595

boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NXP_ADSP_RT595
+
+config BOARD
+	default "nxp_adsp_rt595"
+
+endif # BOARD_NXP_ADSP_RT595

boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023 Google LLC.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <mem.h>
+#include <xtensa/xtensa.dtsi>
+
+/ {
+	model = "nxp_adsp_rt595";
+	compatible = "nxp";
+
+	soc {
+		cpus {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cpu0: cpu@0 {
+				device_type = "cpu";
+				compatible = "cdns,tensilica-xtensa-lx6";
+				reg = <0>;
+			};
+		};
+
+		sram0: memory@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			device_type = "memory";
+			compatible = "mmio-sram";
+			/* Reserve first 512kB of shared memory for ADSP. */
+			reg = <0x0 DT_SIZE_K(512)>;
+			/* Reset section must always be at 0 and at least 1kB. */
+			adsp_reset: memory@0 {
+				reg = <0x0 DT_SIZE_K(1)>;
+			};
+			/* Code and data sections can be moved around and resized if needed. */
+			adsp_text: memory@400 {
+				reg = <0x400 DT_SIZE_K(255)>;
+			};
+			adsp_data: memory@40000 {
+				reg = <0x40000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig

@@ -0,0 +1,7 @@
+CONFIG_SOC_SERIES_NXP_RT595=y
+CONFIG_SOC_NXP_RT595=y
+CONFIG_BOARD_NXP_ADSP_RT595=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y

soc/xtensa/nxp_adsp/CMakeLists.txt

@@ -1,20 +1,26 @@
-# NXP i.MX8 SoC family CMake file
+# NXP i.MX8/RT SoC family CMake file
 #
 # Copyright (c) 2021 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+if(CONFIG_SOC_SERIES_NXP_RT595)
+  zephyr_compile_definitions(CPU_MIMXRT595SFFOC_dsp)
+endif()
+
 add_subdirectory(common)
 
-#  west sign
+if(CONFIG_NXP_ADSP_SIGN_IMAGE)
+  # west sign
 
-# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
-add_custom_target(zephyr.ri ALL
-  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
-)
+  # See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
+  add_custom_target(zephyr.ri ALL
+    DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+  )
 
-add_custom_command(
-  OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
-  COMMENT "west sign --if-tool-available --tool rimage ..."
-  COMMAND  west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
-  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
-)
+  add_custom_command(
+    OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+    COMMENT "west sign --if-tool-available --tool rimage ..."
+    COMMAND  west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
+    DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+  )
+endif()

soc/xtensa/nxp_adsp/Kconfig

@@ -1,4 +1,4 @@
-# NXP i.MX8 SoC family configuration options
+# NXP i.MX8/RT SoC family configuration options
 #
 # Copyright (c) 2021 NXP
 # SPDX-License-Identifier: Apache-2.0
@@ -14,6 +14,10 @@ config SOC_FAMILY
 	string
 	default "nxp_adsp"
 
+config NXP_ADSP_SIGN_IMAGE
+	bool "Sign DSP image with rimage"
+	default y
+
 # Select SoC Part No. and configuration options
 source "soc/xtensa/nxp_adsp/*/Kconfig.soc"
 

soc/xtensa/nxp_adsp/Kconfig.defconfig

@@ -1,9 +1,17 @@
-# NXP i.MX8 SoC family default configuration options
+# NXP i.MX8/RT SoC family default configuration options
 #
 # Copyright (c) 2021 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 source "soc/xtensa/nxp_adsp/*/Kconfig.defconfig.series"
 
 config CACHE_MANAGEMENT
-	def_bool y
+	default y
+
+config XTENSA_TIMER
+	default y
+
+# To prevent test uses TEST_LOGGING_MINIMAL
+config TEST_LOGGING_DEFAULTS
+	default n
+	depends on TEST

soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series

@@ -15,36 +15,16 @@ config SOC
 	string
 	default "nxp_imx8"
 
-config SMP
-	default n
-
-config XTENSA_TIMER
-	default y
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 666000000 if XTENSA_TIMER
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 50000
 
-config KERNEL_ENTRY
-	default "__start"
-
-config MULTI_LEVEL_INTERRUPTS
-	default n
-
-config 2ND_LEVEL_INTERRUPTS
-	default n
-
 config DYNAMIC_INTERRUPTS
 	default y
 
 config LOG
 	default y
 
-# To prevent test uses TEST_LOGGING_MINIMAL
-config TEST_LOGGING_DEFAULTS
-	default n
-	depends on TEST
-
 endif # SOC_SERIES_NXP_IMX8

soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series

@@ -11,44 +11,20 @@ config SOC_TOOLCHAIN_NAME
 	string
 	default "nxp_imx8m_adsp"
 
-# if SOC_MIMX8M_ADSP
-
 config SOC
 	string
 	default "mimx8ml8"
 
-config SMP
-	default n
-
-config XTENSA_TIMER
-	default y
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 800000000 if XTENSA_TIMER
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 50000
 
-config KERNEL_ENTRY
-	default "__start"
-
-config MULTI_LEVEL_INTERRUPTS
-	default n
-
-config 2ND_LEVEL_INTERRUPTS
-	default n
-
 config DYNAMIC_INTERRUPTS
 	default y
 
 config LOG
 	default y
 
-# To prevent test uses TEST_LOGGING_MINIMAL
-config TEST_LOGGING_DEFAULTS
-	default n
-	depends on TEST
-
-# endif # SOC_MIMX8M_ADSP
-
 endif # SOC_SERIES_NXP_IMX8M

soc/xtensa/nxp_adsp/rt595/Kconfig.defconfig.series

@@ -0,0 +1,46 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NXP_RT595
+
+config SOC_SERIES
+	string
+	default "rt595"
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "nxp_rt595"
+
+config SOC
+	string
+	default "nxp_rt595"
+
+config SOC_PART_NUMBER
+	string
+	default "MIMXRT595SFFOC_dsp" if SOC_NXP_RT595
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 198000000
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config DYNAMIC_INTERRUPTS
+	default n
+
+config CACHE
+	default n
+
+config DCACHE
+	default n
+
+config CACHE_MANAGEMENT
+	default n
+
+config LOG
+	default n
+
+config NXP_ADSP_SIGN_IMAGE
+	default n
+
+endif # SOC_SERIES_NXP_RT595

soc/xtensa/nxp_adsp/rt595/Kconfig.series

@@ -0,0 +1,12 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NXP_RT595
+	bool "NXP RT595 Series"
+	select SOC_FAMILY_NXP_ADSP
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	help
+	  NXP RT595 ADSP Series

soc/xtensa/nxp_adsp/rt595/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Google LLC.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "NXP RT595 ADSP SoC Selection"
+
+	config SOC_NXP_RT595
+		bool "NXP RT595"
+		depends on SOC_SERIES_NXP_RT595
+endchoice