boards: SiFive HiFive1 board

Added support for the HiFive1 board from SiFive

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>

boards/riscv32/hifive1/CMakeLists.txt

@@ -0,0 +1,4 @@
+zephyr_library()
+zephyr_library_sources(pinmux.c)
+zephyr_library_sources(clock.c)
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)

boards/riscv32/hifive1/Kconfig.board

@@ -0,0 +1,3 @@
+config BOARD_HIFIVE1
+	bool "HiFive1 target"
+	depends on SOC_RISCV32_FE310

boards/riscv32/hifive1/Kconfig.defconfig

@@ -0,0 +1,6 @@
+if BOARD_HIFIVE1
+
+config BOARD
+	default "hifive1"
+
+endif

boards/riscv32/hifive1/board.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ * Copyright (c) 2017 Palmer Dabbelt <palmer@dabbelt.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/*
+ * UART clock configurations
+ *
+ * Define them here so that it can be replaced by global variables
+ * on other boards where the uart clock is determined dynamically
+ * following the PLL configuration
+ */
+#define uart_fe310_port_0_clk_freq    16000000
+#define uart_fe310_port_1_clk_freq    16000000
+
+/* LEDS configuration */
+#define LED0_GPIO_PORT        "gpio0"
+#define LED1_GPIO_PORT        "gpio0"
+#define LED2_GPIO_PORT        "gpio0"
+
+#define LED0_GPIO_PIN         19
+#define LED1_GPIO_PIN         21
+#define LED2_GPIO_PIN         22
+
+#endif /* __INC_BOARD_H */

boards/riscv32/hifive1/clock.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ * Copyright (c) 2017 Palmer Dabbelt <palmer@dabbelt.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <board.h>
+#include "prci.h"
+
+/* Selects the 16MHz oscilator on the HiFive1 board, which provides a clock
+ * that's accurate enough to actually drive serial ports off of.
+ */
+static int hifive1_clock_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	PRCI_REG(PRCI_PLLCFG) = PLL_REFSEL(1) | PLL_BYPASS(1);
+	PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+	PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+	PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
+	return 0;
+}
+
+SYS_INIT(hifive1_clock_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

boards/riscv32/hifive1/doc/hifive1.rst

@@ -0,0 +1,69 @@
+.. _hifive1:
+
+SiFive HiFive1
+##############
+
+Overview
+********
+
+The HiFive1 is an Arduino-compatible development board with
+an FE310 RISC-V SoC.
+More information can be found on
+`SiFive's wesite <https://www.sifive.com/products/hifive1>`_.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``HiFive1`` board configuration can be built as usual
+(see :ref:`build_an_application`).
+In order to build the application for ``HiFive1``, set the ``BOARD`` variable
+to ``hifive1``.
+
+.. code-block:: bash
+
+   export BOARD="hifive1"
+
+Flashing
+========
+
+In order to upload the application to the device, you'll need OpenOCD and GDB
+with RISC-V support.
+Download and installation instructions can be found in the
+`SiFive's Freedom-E-SDK GitHub repository
+<https://github.com/sifive/freedom-e-sdk>`_.
+
+With the necessary tools installed, you can connect to the board using OpenOCD.
+To establish an OpenOCD connection, switch to the
+:file:`utils` directory and run:
+
+.. code-block:: bash
+
+   # assuming that the location of the openocd is in PATH
+   sudo openocd -f ${SDK_PATH}/bsp/env/freedom-e300-hifive1/openocd.cfg
+
+
+Leave it running, and in a different terminal, use GDB to upload the binary to
+the board. Use the RISC-V GDB from SiFive's Freedom-E-SDK toolchain.
+
+Before loading the binary image to the device, the device's flash protection
+must be disabled. Here are the GDB terminal commands to connect to the device,
+disable the flash protection, load the binary, and start it running:
+
+.. code-block:: console
+
+   gdb
+   (gdb) set remotetimeout 240
+   (gdb) target extended-remote localhost:3333
+   (gdb) monitor reset halt
+   (gdb) monitor flash protect 0 64 last off
+   (gdb) load {path to repository}/build/zephyr/zephyr.elf
+   (gdb) monitor resume
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+

boards/riscv32/hifive1/hifive1_defconfig

@@ -0,0 +1,20 @@
+CONFIG_RISCV32=y
+CONFIG_SOC_SERIES_RISCV32_FE310=y
+CONFIG_SOC_RISCV32_FE310=y
+CONFIG_BOARD_HIFIVE1=y
+CONFIG_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_SERIAL=y
+CONFIG_UART_FE310=y
+CONFIG_UART_FE310_PORT_0=y
+CONFIG_UART_FE310_PORT_0_BAUD_RATE=115200
+CONFIG_UART_FE310_PORT_0_NAME="uart0"
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
+CONFIG_PLIC_FE310=y
+CONFIG_PINMUX=y
+CONFIG_PINMUX_FE310=y
+CONFIG_RISCV_MACHINE_TIMER=y
+CONFIG_GPIO=y
+CONFIG_GPIO_FE310=y
+CONFIG_BOOT_BANNER=y

boards/riscv32/hifive1/pinmux.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <pinmux.h>
+#include <board.h>
+
+static int hifive1_pinmux_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	struct device *p = device_get_binding(CONFIG_PINMUX_FE310_0_NAME);
+
+	/* UART0 RX */
+	pinmux_pin_set(p, 16, FE310_PINMUX_IOF0);
+
+	/* UART0 TX */
+	pinmux_pin_set(p, 17, FE310_PINMUX_IOF0);
+
+	/* SPI1 */
+	pinmux_pin_set(p, 2, FE310_PINMUX_IOF0); /* SS0 */
+	pinmux_pin_set(p, 3, FE310_PINMUX_IOF0); /* MOSI */
+	pinmux_pin_set(p, 4, FE310_PINMUX_IOF0); /* MISO */
+	pinmux_pin_set(p, 5, FE310_PINMUX_IOF0); /* SCK */
+	pinmux_pin_set(p, 9, FE310_PINMUX_IOF0); /* SS2 */
+	pinmux_pin_set(p, 10, FE310_PINMUX_IOF0); /* SS3 */
+
+	return 0;
+}
+
+SYS_INIT(hifive1_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

boards/riscv32/hifive1/prci.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2017 SiFive Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SIFIVE_PRCI_H
+#define _SIFIVE_PRCI_H
+
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
+
+/* Register offsets */
+
+#define PRCI_HFROSCCFG   (0x0000)
+#define PRCI_HFXOSCCFG   (0x0004)
+#define PRCI_PLLCFG      (0x0008)
+#define PRCI_PLLDIV      (0x000C)
+#define PRCI_PROCMONCFG  (0x00F0)
+
+/* Fields */
+#define ROSC_DIV(x)    (((x) & 0x2F) << 0)
+#define ROSC_TRIM(x)   (((x) & 0x1F) << 16)
+#define ROSC_EN(x)     (((x) & 0x1) << 30)
+#define ROSC_RDY(x)    (((x) & 0x1) << 31)
+
+#define XOSC_EN(x)     (((x) & 0x1) << 30)
+#define XOSC_RDY(x)    (((x) & 0x1) << 31)
+
+#define PLL_R(x)       (((x) & 0x7)  << 0)
+/* single reserved bit for F LSB. */
+#define PLL_F(x)       (((x) & 0x3F) << 4)
+#define PLL_Q(x)       (((x) & 0x3)  << 10)
+#define PLL_SEL(x)     (((x) & 0x1)  << 16)
+#define PLL_REFSEL(x)  (((x) & 0x1)  << 17)
+#define PLL_BYPASS(x)  (((x) & 0x1)  << 18)
+#define PLL_LOCK(x)    (((x) & 0x1)  << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+
+#define PLL_REFSEL_HFROSC 0x0
+#define PLL_REFSEL_HFXOSC 0x1
+
+#define PLL_SEL_HFROSC 0x0
+#define PLL_SEL_PLL    0x1
+
+#define PLL_FINAL_DIV(x)      (((x) & 0x3F) << 0)
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1) << 8)
+
+#define PROCMON_DIV(x)   (((x) & 0x1F) << 0)
+#define PROCMON_TRIM(x)  (((x) & 0x1F) << 8)
+#define PROCMON_EN(x)    (((x) & 0x1)  << 16)
+#define PROCMON_SEL(x)   (((x) & 0x3)  << 24)
+#define PROCMON_NT_EN(x) (((x) & 0x1)  << 28)
+
+#define PROCMON_SEL_HFCLK     0
+#define PROCMON_SEL_HFXOSCIN  1
+#define PROCMON_SEL_PLLOUTDIV 2
+#define PROCMON_SEL_PROCMON   3
+
+#endif /* _SIFIVE_PRCI_H */