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soc: arm: atmel_sam: sam4e: Rework clock_init
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Update clock_init for the Atmel SAM4E SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
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@pdgendt
pdgendt committed Dec 27, 2023
1 parent f2eb369 commit 9677186
Showing 1 changed file with 44 additions and 131 deletions.
175 changes: 44 additions & 131 deletions soc/arm/atmel_sam/sam4e/soc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023 Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -15,9 +16,9 @@
* for the Atmel SAM4E series processor.
*/

#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <soc_pmc.h>
#include <soc_supc.h>

/**
* @brief Setup various clock on SoC at boot time.
Expand All @@ -29,126 +30,57 @@
*/
static ALWAYS_INLINE void clock_init(void)
{
uint32_t reg_val;
/* Switch the main clock to the internal OSC with 12MHz */
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);

#ifdef CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK
/* Switch slow clock to the external 32 KHz crystal oscillator. */
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
/* Switch MCK (Master Clock) to the main clock */
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);

/* Wait for oscillator to be stabilized. */
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
;
}

#endif /* CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK */
EFC->EEFC_FMR = EEFC_FMR_FWS(0);

#ifdef CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK
/*
* Setup main external crystal oscillator.
*/
soc_pmc_enable_clock_failure_detector();

/* Start the external crystal oscillator. */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
/* Fast RC oscillator frequency is at 4 MHz. */
| CKGR_MOR_MOSCRCF_4_MHz
/*
* We select maximum setup time. While start up time
* could be shortened this optimization is not deemed
* critical right now.
*/
| CKGR_MOR_MOSCXTST(0xFFu)
/* RC oscillator must stay on. */
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;

/* Wait for oscillator to be stabilized. */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
;
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}

/* Select the external crystal oscillator as the main clock source. */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCRCF_4_MHz
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCSEL;

/* Wait for external oscillator to be selected. */
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
;
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/

/* Turn off RC oscillator, not used any longer, to save power */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCXTEN;
/* We select maximum setup time.
* While start up time could be shortened
* this optimization is not deemed
* critical now.
*/
soc_pmc_switch_mainck_to_xtal(false, 0xff);

/* Wait for the RC oscillator to be turned off. */
while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
;
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG.
*/
soc_pmc_enable_waitmode();
}
}

#ifdef CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG.
*/
PMC->PMC_FSMR |= PMC_FSMR_LPM;
#endif
#else
/* Setup main fast RC oscillator. */

/*
* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
* register, should normally be the case.
* Set FWS (Flash Wait State) value before increasing Master Clock
* (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
* This is set to the highest number of read cycles because it won't
* hurt lower clock frequencies. However, a high frequency with too
* few read cycles could cause flash read problems. FWS 5 (6 cycles)
* is the safe setting for all of this SoCs usable frequencies.
*/
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}

/* Set main fast RC oscillator to 12 MHz. */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCRCF_12_MHz
| CKGR_MOR_MOSCRCEN;

/* Wait for RC oscillator to stabilize. */
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK */
EFC->EEFC_FMR = EEFC_FMR_FWS(5);

/*
* Setup PLLA
*/

/* Switch MCK (Master Clock) to the main clock first. */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;

/* Wait for clock selection to complete. */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}

/* Setup PLLA. */
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
| CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA)
| CKGR_PLLAR_PLLACOUNT(0x3Fu)
| CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA);

/*
* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
* otherwise PLL will be disabled. In this case we would get stuck in
* the following loop.
*/

/* Wait for PLL lock. */
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
;
}
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA);

/*
* Final setup of the Master Clock
Expand All @@ -159,38 +91,19 @@ static ALWAYS_INLINE void clock_init(void)
* If CSS or PRES are modified we must wait for MCKRDY bit to be
* set again.
*/
soc_pmc_mck_set_prescaler(1);

/* Setup prescaler - PLLA Clock / Processor Clock (HCLK). */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;

/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}

/* Finally select PLL as Master Clock source. */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
/* Select PLL as Master Clock source. */
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);

/* Wait for Master Clock setup to complete. */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}

void z_arm_platform_init(void)
{
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
* (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
* This is set to the highest number of read cycles because it won't
* hurt lower clock frequencies. However, a high frequency with too
* few read cycles could cause flash read problems. FWS 5 (6 cycles)
* is the safe setting for all of this SoCs usable frequencies.
*/
EFC->EEFC_FMR = EEFC_FMR_FWS(5);

/* Setup system clocks. */
clock_init();
}

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