drivers: clock_control: define max clock freq for STM32H7B0

Define max **SYSCLK** and **AHB** clock frequencies as 280 MHz, and max **APB** frequency as 140 MHz. Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
zephyrproject-rtos · Nov 11, 2023 · c2a1398 · c2a1398
1 parent 9ba871e
commit c2a1398
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -107,7 +107,8 @@
 #define AHB_FREQ_MAX		275000000UL
 #define APBx_FREQ_MAX		137500000UL
 #elif defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) ||\
-	  defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
+	  defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ) ||\
+	  defined(CONFIG_SOC_STM32H7B0XX) || defined(CONFIG_SOC_STM32H7B0XXQ)
 #define SYSCLK_FREQ_MAX		280000000UL
 #define AHB_FREQ_MAX		280000000UL
 #define APBx_FREQ_MAX		140000000UL