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boards: rv32m1_vega: Introduce zero-riscy configuration

Introduces a new rv32m1_vega board configuration for the zero-riscy
core. It assumes that the soc has been reconfigured with openocd to boot
to the zero-riscy core instead of the ri5cy core.

Refactors the board-level device tree so the ri5cy and zero-riscy
configurations share common definitions for the led, button, and sensor
nodes.

Tested with:
- samples/hello_world
- samples/synchronization
- samples/basic/blinky
- samples/basic/button
- samples/sensor/fxos8700

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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MaureenHelm authored and galak committed Apr 17, 2019
1 parent 948ef47 commit cf1d374276928ec0a77e3a7537cbc331ba22361f
@@ -27,8 +27,9 @@ flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
coprocessor for applications running on RI5CY. The two cores can
communicate via shared memory and messaging peripherals.

Currently, Zephyr only supports RI5CY with the ``rv32m1_vega_ri5cy``
board configuration name. Support for ZERO-RISCY is planned.
Currently, Zephyr supports RI5CY with the ``rv32m1_vega_ri5cy`` board
configuration name, and ZERO_RISCY with the ``rv32m1_vega_zero_riscy`` board
configuration name.

Hardware
********
@@ -91,6 +92,30 @@ the following hardware features:
| | | fxos8700 trigger; |
+-----------+------------+-------------------------------------+

Zephyr's ZERO-RISCY configuration, ``rv32m1_vega_zero_riscy``, currently
supports the following hardware features:

+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| EVENT | on-chip | event unit interrupt controller |
+-----------+------------+-------------------------------------+
| INTMUX | on-chip | level 2 interrupt controller |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | lptmr-based system timer |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger; |
+-----------+------------+-------------------------------------+

Connections and IOs
===================

@@ -251,26 +276,28 @@ Additional Pins
For an up-to-date description of additional pins (such as buttons,
LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr
source code, i.e.
:zephyr_file:`boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts` for RI5CY.
:zephyr_file:`boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts` for RI5CY and
:zephyr_file:`boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts` for
ZERO-RISCY.

See the schematic in the documentation available from the `OpenISA
GitHub releases`_ page for additional details.

System Clocks
=============

The RI5CY core is configured to use the slow internal reference clock
(SIRC) as the clock source for an LPTMR peripheral to manage the
system timer, and the fast internal reference clock (FIRC) to generate
a 48MHz core clock.
The RI5CY and ZERO-RISCY cores are configured to use the slow internal
reference clock (SIRC) as the clock source for an LPTMR peripheral to manage
the system timer, and the fast internal reference clock (FIRC) to generate a
48MHz core clock.

Serial Port
===========

The USB connector at the top left of the board (near the RESET button)
is connected to an OpenSDA chip which provides a serial USB
device. This is connected to the LPUART0 peripheral which the RI5CY
core uses by default for console and logging.
The USB connector at the top left of the board (near the RESET button) is
connected to an OpenSDA chip which provides a serial USB device. This is
connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by
default for console and logging.

.. warning::

@@ -403,15 +430,15 @@ debugger and adapter board. See the :ref:`above information

#. Make sure your J-Link is connected to your computer via USB.

One-Time Board Setup For Booting RI5CY
======================================
One-Time Board Setup For Booting RI5CY or ZERO-RISCY
====================================================

Next, you'll need to make sure your board boots the RI5CY core. **You
only need to do this once.**
Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core.
**You only need to do this once.**

The RV32M1 SoC on the VEGAboard has multiple cores, any of which can
be selected as the boot core. Before flashing and debugging, you'll
first make sure you're booting RI5CY.
first make sure you're booting the right core.

**Linux and macOS**:

@@ -455,6 +482,9 @@ first make sure you're booting RI5CY.
> init
> ri5cy_boot

To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
``zero_boot``.

The reset button is at top left, as shown in the following figure.

.. figure:: ri5cy_boot.jpg
@@ -480,6 +510,9 @@ In a telnet program of your choice:
#. Quit the OpenOCD and telnet sessions.
#. Unplug your J-Link and VEGAboard, and plug them back in.

To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with
``zero_boot``.

Compiling a Program
===================

@@ -0,0 +1,79 @@
/*
* Copyright 2018 Foundries.io Ltd
* SPDX-License-Identifier: Apache-2.0
*/

/ {
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
led3 = &sts_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
sw2 = &user_button_4;
sw3 = &user_button_5;
};

leds {
compatible = "gpio-leds";
blue_led: led_0 {
gpios = <&gpioa 22 0>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpioa 23 0>;
label = "User LD2";
};
red_led: led_2 {
gpios = <&gpioa 24 0>;
label = "User LD3";
};
sts_led: led_3 {
gpios = <&gpioe 0 0>;
label = "User LD4";
};
};

gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioa 0 GPIO_INT_ACTIVE_LOW>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpioe 8 GPIO_INT_ACTIVE_LOW>;
};
user_button_4: button_2 {
label = "User SW4";
gpios = <&gpioe 9 GPIO_INT_ACTIVE_LOW>;
};
user_button_5: button_3 {
label = "User SW5";
gpios = <&gpioe 12 GPIO_INT_ACTIVE_LOW>;
};
};
};

&uart0 {
current-speed = <115200>;
status = "ok";
};

arduino_i2c: &i2c0 {
status = "ok";
};

&i2c3 {
status = "ok";

fxos8700@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
label = "FXOS8700";
reset-gpios = <&gpioe 27 0>;
int1-gpios = <&gpioe 1 0>;
int2-gpios = <&gpioe 22 0>;
};
};
@@ -6,87 +6,15 @@
/dts-v1/;

#include "rv32m1_ri5cy.dtsi"
#include "rv32m1_vega.dtsi"

/ {
model = "OpenISA RV32M1 Vega RI5CY";
compatible = "openisa,rv32m1";

aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
led3 = &sts_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
sw2 = &user_button_4;
sw3 = &user_button_5;
};

chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,uart-pipe = &uart0;
};

leds {
compatible = "gpio-leds";
blue_led: led_0 {
gpios = <&gpioa 22 0>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpioa 23 0>;
label = "User LD2";
};
red_led: led_2 {
gpios = <&gpioa 24 0>;
label = "User LD3";
};
sts_led: led_3 {
gpios = <&gpioe 0 0>;
label = "User LD4";
};
};

gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioa 0 GPIO_INT_ACTIVE_LOW>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpioe 8 GPIO_INT_ACTIVE_LOW>;
};
user_button_4: button_2 {
label = "User SW4";
gpios = <&gpioe 9 GPIO_INT_ACTIVE_LOW>;
};
user_button_5: button_3 {
label = "User SW5";
gpios = <&gpioe 12 GPIO_INT_ACTIVE_LOW>;
};
};
};

&uart0 {
current-speed = <115200>;
status = "ok";
};

arduino_i2c: &i2c0 {
status = "ok";
};

&i2c3 {
status = "ok";

fxos8700@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
label = "FXOS8700";
reset-gpios = <&gpioe 27 0>;
int1-gpios = <&gpioe 1 0>;
int2-gpios = <&gpioe 22 0>;
};
};
@@ -0,0 +1,20 @@
/*
* Copyright 2018 Foundries.io Ltd
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include "rv32m1_zero_riscy.dtsi"
#include "rv32m1_vega.dtsi"

/ {
model = "OpenISA RV32M1 Vega Zero RISCY";
compatible = "openisa,rv32m1";

chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,uart-pipe = &uart0;
};
};
@@ -0,0 +1,9 @@
identifier: rv32m1_vega_zero_riscy
name: RV32M1-VEGA
type: mcu
arch: riscv32
toolchain:
- cross-compile
- zephyr
supported:
- i2c
@@ -0,0 +1,12 @@
CONFIG_RISCV32=y
CONFIG_SOC_OPENISA_RV32M1_RISCV32=y
CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y
CONFIG_BOARD_RV32M1_VEGA=y
CONFIG_CLOCK_CONTROL_RV32M1_PCC=y
CONFIG_GPIO=y
CONFIG_PINMUX=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_MULTI_LEVEL_INTERRUPTS=y

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