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tests/kernel/interrupt fails on quark_se_c1000_ss_devboard #12147

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spoorthik opened this issue Dec 18, 2018 · 0 comments
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tests/kernel/interrupt fails on quark_se_c1000_ss_devboard #12147

spoorthik opened this issue Dec 18, 2018 · 0 comments
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bug The issue is a bug, or the PR is fixing a bug

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@spoorthik
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Describe the bug
Assertion failure on quark_se_c1000_ss_devboard as the test assigns IRQ priority greater than max limit.

To Reproduce
Steps to reproduce the behavior:

  1. mkdir build; cd build
  2. cmake -DBOARD=quark_se_c1000_ss_devboard
  3. make
  4. See error

Screenshots or console output

***** Booting Zephyr OS zephyr-v1.13.0-2813-ga8ce329 (delayed boot 1000ms) *****
Running test suite interrupt_feature
===================================================================
starting test - test_nested_isr
ASSERTION FAIL [prio < 2] @ /home/kspoorth/work/latest_zephyr/arch/arc/core/irq_manage.c:85
        invalid priority 2 for irq 66

Environment (please complete the following information):

  • OS: Linux
  • Toolchain: Zephyr SDK 0.9.5
@spoorthik spoorthik added the bug The issue is a bug, or the PR is fixing a bug label Dec 18, 2018
@spoorthik spoorthik mentioned this issue Dec 18, 2018
Merged
spoorthik added a commit to spoorthik/zephyr that referenced this issue Dec 20, 2018
@spoorthik
tests: interrupt: Change IRQ priorities in test
0970ca0 
Keeping IRQ0 priority as 1 and IRQ1 priority as 0
so that system timer which of priority 0 in ARC
will be interrupted by IRQ1 of same priority.
In ARM, system timer is of priority 1, hence
making ISR0 priority as 2 and ISR1 priority as 1.
Thus system timer will always be interrupted by
ISR1 in both the architectures.

Fixes: zephyrproject-rtos#12147

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
carlescufi pushed a commit that referenced this issue Dec 21, 2018
@spoorthik @carlescufi
tests: interrupt: Change IRQ priorities in test
e62e54b 
Keeping IRQ0 priority as 1 and IRQ1 priority as 0
so that system timer which of priority 0 in ARC
will be interrupted by IRQ1 of same priority.
In ARM, system timer is of priority 1, hence
making ISR0 priority as 2 and ISR1 priority as 1.
Thus system timer will always be interrupted by
ISR1 in both the architectures.

Fixes: #12147

Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
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