ISR sometimes run with the MPU disabled: breaks __nocache #12548
Labels
area: ARM
ARM (32-bit) Architecture
area: Memory Protection
bug
The issue is a bug, or the PR is fixing a bug
priority: medium
Medium impact/importance bug
Milestone
Describe the bug
On ARM platforms with and
CONFIG_CPU_HAS_ARM_MPU=y
andCONFIG_MPU_STACK_GUARD=y
, the ISR might sometimes (but rarely) run with the MPU disabled.This happens because the MPU is briefly disabled and then re-enabled in
configure_mpu_stack_guard
, which is called during context switch:zephyr/arch/arm/core/cortex_m/mpu/arm_core_mpu.c
Lines 38 to 41 in 962f900
If an interrupt happens during this small amount of time, it runs with the MPU disabled. The MPU is used by the __nocache feature to disable cache on a memory region. When the MPU is disabled, the cache is enabled again. Access to this regions therefore sometimes returns stale data from the previous time the cache was enabled.
The workaround it to set
CONFIG_MPU_STACK_GUARD=n
andCONFIG_USERSPACE=n
. This avoid the MPU to be disabled and re-enabled during context switch.To Reproduce
This was observed when working on PR #11888. The problem happens when doing multi-Mb transfer on the ethernet interface, therefore causing a lot of interrupts. I used this debug code in the interrupt, I guess it can also be reproduced with other interrupts:
Expected behavior
The MPU is always enabled when running ISR code.
Impact
This breaks __nocache support, which in turns prevents to enable cache on SAM E70 when the ethernet driver is enabled (PR #11888).
Environment (please complete the following information):
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