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SPI speed when using SDHC via SPI in Zephyr #32996

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DrEdHepler opened this issue Mar 5, 2021 · 0 comments · Fixed by #33684
Closed

SPI speed when using SDHC via SPI in Zephyr #32996

DrEdHepler opened this issue Mar 5, 2021 · 0 comments · Fixed by #33684
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@jfischer-no
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area: Disk Access area: Drivers bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug

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@DrEdHepler
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I'm using the Nordic nRF52840-DK board to breadboard an SDHC card interface in Zephyr using SPI. I have it doing "basic" operations, but am trying to reconcile what I'm physically seeing versus what is documented and what I see in the code. I was hoping to run the SPI at 8 MHz, so I included a statement in the .overlay file: clock-frequency = <8000000>; in the SPI specification. I also put the statement: spi-max-frequency = <8000000>; in the specification of the SDcard sub-device (under the SPI specification). The Zephyr SDHC documentation page seems to imply that the spi-max-frequency parameter is the SPI running frequency applied after initialization. But it appears that hardcoded into disk_access_spi_sdhc.c are statements that assign the speed to be 400 KHz during initialization, then 4 MHz for later operations. But then looking at the waveform captured by a logic analyzer, it appears that the SCK signal is actually running at around 250 KHz. What am I missing? Thanks!
@jfischer-no jfischer-no self-assigned this Mar 12, 2021
@jfischer-no jfischer-no added area: Disk Access area: Drivers bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug labels Mar 12, 2021
@jfischer-no jfischer-no mentioned this issue Mar 24, 2021
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@richardbarlow richardbarlow mentioned this issue Mar 24, 2021
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richardbarlow pushed a commit to richardbarlow/zephyr that referenced this issue Mar 26, 2021
disk: sdhc: Switch to clock frequency from DTS
ee52000 
The "spi-max-frequency" property already exists, but was unused. This
now sets the SPI clock frequency to this value (limited to 24MHz) once
initialisation is complete.

Due to the nature of the SPI API, it is necessary to have two separate
configuration structures to switch clock speed as some SPI drivers only
compare pointers to detect changes.

Fixes: zephyrproject-rtos#32996

Signed-off-by: Rich Barlow <rich@bennellick.com>
nashif pushed a commit that referenced this issue Mar 26, 2021
@nashif
disk: sdhc: Switch to clock frequency from DTS
9f2a65e 
The "spi-max-frequency" property already exists, but was unused. This
now sets the SPI clock frequency to this value (limited to 24MHz) once
initialisation is complete.

Due to the nature of the SPI API, it is necessary to have two separate
configuration structures to switch clock speed as some SPI drivers only
compare pointers to detect changes.

Fixes: #32996

Signed-off-by: Rich Barlow <rich@bennellick.com>
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area: Disk Access area: Drivers bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug
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disk: sdhc: Switch to clock frequency from DTS richardbarlow/zephyr
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@DrEdHepler @jfischer-no