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usdhc disk_usdhc_access_write busy fail #39942
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@lgl88911 I've reproduced the bug on my end. The issue results from poor support for 1.8V SD card signalling in NXP's USDHC driver. This is likely the same root cause as #32289 The latest version of main has this pr applied, as a temporary fix. I tested your fix as well, and it will resolve the issue. However, since our SDK USDHC driver does not use a |
Yes, I tested it on mm_swiftio and mm_feather,can reproduce it .
Do you mean that using
I agree, I think this is more like hardware of SOC instability. I did some tracking: The following is a simplified process of calling code when something goes wrong
In addition, under mm_swiftio(with |
This is interesting. I have not been able to reproduce the issue on an RT1050 EVK with
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@danieldegrasse I tested a total of 7 cards from 4 manufacturers, and one of them is a card that does not support 1.8V, but this problem will occur no matter which one.
Does it refer to this #39114 ? |
@lgl88911 It does, yes. I tested your temporary patch on an RT1050 when the |
@danieldegrasse Thanks, I test #40522 on MadMachine board, It can solve this problem. I think you have found the root cause:
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USDHC driver did not pass disk test (failed during multiple writes). Add logic to wait for the SD card to be idle before reading new data, so that the test will pass. Also, add logic to reject OOB reads and writes to the disk. Fixes zephyrproject-rtos#39942 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
USDHC driver did not pass disk test (failed during multiple writes). Add logic to wait for the SD card to be idle before reading new data, so that the test will pass. Also, add logic to reject OOB reads and writes to the disk. Fixes #39942 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Describe the bug
disk_usdhc_access_write fail because CDIHB reports busy fail
To Reproduce
Test on rt1052, Zephyr V2.7.0 & V2.4.0
Additional context
For unknown reasons, calling disk_usdhc_access_write continuously will check that the CDIHB field of the register PRES_STATE is 1 after the previous transfer is completed and before the next transfer. This phenomenon is more likely to occur. May be a SOC issue, and more experiments are needed to confirm.
Below is a temporary patch:
madmachineio@5034b84
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