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Wrong clock assigned #48367

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JeroenReeskamp opened this issue Jul 27, 2022 · 0 comments · Fixed by #49196
Closed

Wrong clock assigned #48367

JeroenReeskamp opened this issue Jul 27, 2022 · 0 comments · Fixed by #49196
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@dleach02
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bug The issue is a bug, or the PR is fixing a bug platform: NXP NXP priority: low Low impact/importance bug

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@JeroenReeskamp
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zephyr/drivers/clock_control/clock_control_mcux_syscon.c

Lines 95 to 103 in 3b5590a

case MCUX_HS_SPI_CLK:
#if defined(SYSCON_HSLSPICLKSEL_SEL_MASK)
*rate = CLOCK_GetHsLspiClkFreq();
#else
*rate = CLOCK_GetFlexCommClkFreq(14);
#endif
case MCUX_HS_SPI1_CLK:
*rate = CLOCK_GetFlexCommClkFreq(16);
break;

In the case of MCUX_HS_SPI_CLK the switch always falls trough and you end up with MCUX_HS_SPI1_CLK, is this intentional? Or should a break be added after line 100?
@galak galak added the platform: NXP NXP label Jul 28, 2022
@dleach02 dleach02 added bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug labels Aug 4, 2022
decsny added a commit to nxp-zephyr/zephyr that referenced this issue Aug 17, 2022
@decsny
drivers: Fixes MCUX clock assignment
9a72b80 
In clock_control_mcux_syscon.c,
add a break statement.

Fixes zephyrproject-rtos#48367

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
@decsny decsny mentioned this issue Aug 17, 2022
Merged
galak pushed a commit that referenced this issue Aug 17, 2022
@decsny @galak
drivers: Fixes MCUX clock assignment
84f3a0a 
In clock_control_mcux_syscon.c,
add a break statement.

Fixes #48367

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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@dleach02 dleach02

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bug The issue is a bug, or the PR is fixing a bug platform: NXP NXP priority: low Low impact/importance bug
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drivers: Fixes MCUX clock assignment nxp-zephyr/zephyr
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@galak @dleach02 @JeroenReeskamp