RISCV: fpu_sharing mode

[SJC0719]

In the isr.S file in the riscv directory, after the fpu_sharling function is enabled, the system reads the value of the csr register mcause to determine whether the current exception belongs to the fpu operation. In this file, the system directly compares the value of mcause with that of 2 to determine whether to enter the jump. However, the actual mcause value is only used to determine the low 7bit, other bits may exist other values, resulting in the program can not jump normally

`

/* determine if FPU access was disabled */

li t1, MSTATUS_FS

and t1, t1, t2

bnez t1, no_fp

/* determine if this is an Illegal Instruction exception */

csrr t2, mcause

and t2,t2,SOC_MCAUSE_EXP_MASK      //The low exception number should be performed or operated on here

li t1, 2		/* 2 = illegal instruction */

bne t1, t2, no_fp

/* determine if we trapped on an FP instruction. */

csrr t2, mtval		/* get faulting instruction */

`

[github-actions]

Hi @SJC0719! We appreciate you submitting your first issue for our open-source project. 🌟

Even though I'm a bot, I can assure you that the whole community is genuinely grateful for your time and effort. 🤖💙

[aescolar]

@SJC0719 Please use the template when filling issues

[fkokosinski]

Hey @npitre, could you perhaps take a look at this?