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Add driver support for ADC1 of stm32 #13447

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merged 5 commits into from
May 8, 2019
Merged

Add driver support for ADC1 of stm32 #13447

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7e8f8f6
dts: arm: stm32: add dts support for ADC1 of stm32
cybertale May 7, 2019
2ae1f39
drivers: pinmux: stm32: add pinmux support for ADC of stm32
cybertale May 7, 2019
85d246f
drivers: adc: add driver support for ADC1 of stm32
cybertale May 7, 2019
7b68bc3
test: driver: adc: add some nucleo boards support for adc test cases
cybertale May 7, 2019
9bb471d
doc: boards: arm: nucleo: add ADC support to the boards doc
cybertale May 7, 2019
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2 changes: 2 additions & 0 deletions CODEOWNERS
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Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,7 @@
/drivers/*/*stm32* @erwango
/drivers/*/*native_posix* @aescolar
/drivers/adc/ @anangl
/drivers/adc/adc_stm32.c @cybertale
/drivers/bluetooth/ @joerchan @jhedberg @Vudentz
/drivers/can/ @alexanderwachter
/drivers/can/*mcp2515* @karstenkoenig
Expand Down Expand Up @@ -154,6 +155,7 @@
/dts/riscv32/rv32m1* @MaureenHelm
/dts/bindings/ @galak
/dts/bindings/can/ @alexanderwachter
/dts/bindings/iio/adc/st,stm32-adc.yaml @cybertale
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Please also add drivers/adc/adc_stm32.c

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OK

/dts/bindings/serial/ns16550.yaml @gnuless
/dts/bindings/*/nordic* @anangl
/dts/bindings/*/nxp* @MaureenHelm
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f091rc/doc/index.rst
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Expand Up @@ -96,6 +96,8 @@ The Zephyr nucleo_f091rc board configuration supports the following hardware fea
+-----------+------------+-------------------------------------+
| SPI | on-chip | SPI controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported in this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f091rc/nucleo_f091rc.dts
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Expand Up @@ -93,3 +93,7 @@ arduino_spi: &spi1 {
};
};
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f091rc/nucleo_f091rc.yaml
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Expand Up @@ -15,6 +15,7 @@ supported:
- nvs
- spi
- watchdog
- adc
testing:
ignore_tags:
- net
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3 changes: 3 additions & 0 deletions boards/arm/nucleo_f091rc/pinmux.c
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Expand Up @@ -40,6 +40,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PB14, STM32F0_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F0_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif /* CONFIG_SPI_2 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32F0_PINMUX_FUNC_PA0_ADC_IN0},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f103rb/doc/index.rst
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Expand Up @@ -93,6 +93,8 @@ The Zephyr nucleo_f103rb board configuration supports the following hardware fea
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported in this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f103rb/nucleo_f103rb.dts
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Expand Up @@ -78,3 +78,7 @@ arduino_spi: &spi1 {
&iwdg {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f103rb/nucleo_f103rb.yaml
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Expand Up @@ -13,3 +13,4 @@ supported:
- spi
- pwm
- watchdog
- adc
3 changes: 3 additions & 0 deletions boards/arm/nucleo_f103rb/pinmux.c
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Expand Up @@ -41,6 +41,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PB14, STM32F1_PINMUX_FUNC_PB14_SPI2_MASTER_MISO},
{STM32_PIN_PB15, STM32F1_PINMUX_FUNC_PB15_SPI2_MASTER_MOSI},
#endif /* CONFIG_SPI_2 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32F1_PINMUX_FUNC_PA0_ADC123_IN0},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f207zg/doc/index.rst
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Expand Up @@ -92,6 +92,8 @@ The Zephyr nucleo_207zg board configuration supports the following hardware feat
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f207zg/nucleo_f207zg.dts
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Expand Up @@ -72,3 +72,7 @@ arduino_serial: &usart6 {};
&iwdg {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f207zg/nucleo_f207zg.yaml
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Expand Up @@ -12,3 +12,4 @@ supported:
- gpio
- usb_device
- watchdog
- adc
3 changes: 3 additions & 0 deletions boards/arm/nucleo_f207zg/pinmux.c
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Expand Up @@ -39,6 +39,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PA11, STM32F2_PINMUX_FUNC_PA11_OTG_FS_DM},
{STM32_PIN_PA12, STM32F2_PINMUX_FUNC_PA12_OTG_FS_DP},
#endif /* CONFIG_USB_DC_STM32 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32F2_PINMUX_FUNC_PA0_ADC123_IN0},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f302r8/doc/index.rst
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Expand Up @@ -97,6 +97,8 @@ features:
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f302r8/nucleo_f302r8.dts
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Expand Up @@ -82,3 +82,7 @@ arduino_spi: &spi2 {};
&rtc {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f302r8/nucleo_f302r8.yaml
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Expand Up @@ -16,3 +16,4 @@ supported:
- pwm
- rtc
- counter
- adc
3 changes: 3 additions & 0 deletions boards/arm/nucleo_f302r8/pinmux.c
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Expand Up @@ -39,6 +39,9 @@ static const struct pin_config pinconf[] = {
#ifdef CONFIG_PWM_STM32_2
{STM32_PIN_PA0, STM32F3_PINMUX_FUNC_PA0_PWM2_CH1},
#endif /* CONFIG_PWM_STM32_2 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32F3_PINMUX_FUNC_PA0_ADC1_IN1},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f401re/doc/index.rst
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Expand Up @@ -83,6 +83,8 @@ The Zephyr nucleo_401re board configuration supports the following hardware feat
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on Zephyr porting.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f401re/nucleo_f401re.dts
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Expand Up @@ -117,3 +117,7 @@ arduino_spi: &spi1 {
&rtc {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f401re/nucleo_f401re.yaml
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Expand Up @@ -14,5 +14,6 @@ supported:
- gpio
- i2c
- spi
- adc
ram: 96
flash: 512
3 changes: 3 additions & 0 deletions boards/arm/nucleo_f401re/pinmux.c
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Expand Up @@ -41,6 +41,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32F4_PINMUX_FUNC_PA0_ADC123_IN0},
#endif /* CONFIG_ADC_1 */
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Is this empty #ifdef block intentional?

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Sorry, my mistake

};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_f746zg/doc/index.rst
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Expand Up @@ -118,6 +118,8 @@ features:
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_f746zg/nucleo_f746zg.dts
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Expand Up @@ -108,3 +108,7 @@ arduino_spi: &spi1 {};
phase_seg2 = <5>;
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_f746zg/nucleo_f746zg.yaml
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Expand Up @@ -21,3 +21,4 @@ supported:
- rtc
- counter
- can
- adc
3 changes: 3 additions & 0 deletions boards/arm/nucleo_f746zg/pinmux.c
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Expand Up @@ -66,6 +66,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PD0, STM32F7_PINMUX_FUNC_PD0_CAN_RX},
{STM32_PIN_PD1, STM32F7_PINMUX_FUNC_PD1_CAN_TX},
#endif /* CONFIG_CAN_1 */
#ifdef CONFIG_ADC_1
{ STM32_PIN_PA0, STM32F7_PINMUX_FUNC_PA0_ADC123_IN0 },
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_l073rz/doc/index.rst
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Expand Up @@ -94,6 +94,8 @@ The Zephyr nucleo_l073rz board configuration supports the following hardware fea
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported in this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_l073rz/nucleo_l073rz.dts
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Expand Up @@ -65,3 +65,7 @@ arduino_spi: &spi1 {
&iwdg {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_l073rz/nucleo_l073rz.yaml
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Expand Up @@ -14,3 +14,4 @@ supported:
- i2c
- spi
- watchdog
- adc
3 changes: 3 additions & 0 deletions boards/arm/nucleo_l073rz/pinmux.c
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Expand Up @@ -31,6 +31,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PA6, STM32L0_PINMUX_FUNC_PA6_SPI1_MISO},
{STM32_PIN_PA7, STM32L0_PINMUX_FUNC_PA7_SPI1_MOSI},
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PA0, STM32L0_PINMUX_FUNC_PA0_ADC_IN0},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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2 changes: 2 additions & 0 deletions boards/arm/nucleo_l476rg/doc/index.rst
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Expand Up @@ -123,6 +123,8 @@ The Zephyr nucleo_l476rg board configuration supports the following hardware fea
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on this Zephyr port.

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4 changes: 4 additions & 0 deletions boards/arm/nucleo_l476rg/nucleo_l476rg.dts
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Expand Up @@ -79,3 +79,7 @@ arduino_i2c: &i2c1 {
&rtc {
status = "ok";
};

&adc1 {
status = "ok";
};
1 change: 1 addition & 0 deletions boards/arm/nucleo_l476rg/nucleo_l476rg.yaml
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Expand Up @@ -14,5 +14,6 @@ supported:
- i2c
- rtc
- counter
- adc
ram: 96
flash: 1024
3 changes: 3 additions & 0 deletions boards/arm/nucleo_l476rg/pinmux.c
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Expand Up @@ -60,6 +60,9 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PC11, STM32L4X_PINMUX_FUNC_PC11_SPI3_MISO},
{STM32_PIN_PC12, STM32L4X_PINMUX_FUNC_PC12_SPI3_MOSI},
#endif /* CONFIG_SPI_3 */
#ifdef CONFIG_ADC_1
{STM32_PIN_PC0, STM32L4X_PINMUX_FUNC_PC0_ADC123_IN1},
#endif /* CONFIG_ADC_1 */
};

static int pinmux_stm32_init(struct device *port)
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1 change: 1 addition & 0 deletions drivers/adc/CMakeLists.txt
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Expand Up @@ -9,4 +9,5 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC adc_nrfx_saadc.c)
zephyr_library_sources_ifdef(CONFIG_ADC_INTEL_QUARK_SE_C1000_SS adc_intel_quark_se_c1000_ss.c)
zephyr_library_sources_ifdef(CONFIG_ADC_INTEL_QUARK_D2000 adc_intel_quark_d2000.c)
zephyr_library_sources_ifdef(CONFIG_ADC_SAM0 adc_sam0.c)
zephyr_library_sources_ifdef(CONFIG_ADC_STM32 adc_stm32.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE adc_handlers.c)
2 changes: 2 additions & 0 deletions drivers/adc/Kconfig
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Expand Up @@ -57,4 +57,6 @@ source "drivers/adc/Kconfig.intel_quark"

source "drivers/adc/Kconfig.sam0"

source "drivers/adc/Kconfig.stm32"

endif # ADC
25 changes: 25 additions & 0 deletions drivers/adc/Kconfig.stm32
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@@ -0,0 +1,25 @@
# Kconfig - ADC configuration options

#
# Copyright (c) 2019 Intel Corporation
# Copyright (c) 2019 Endre Karlson
# Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#

menuconfig ADC_STM32
bool "STM32 ADC driver"
depends on SOC_FAMILY_STM32
help
Enable the driver implementation for the stm32xx ADC

if ADC_STM32

config ADC_1
bool "ADC1"
default y
help
Enable ADC1

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Miss ADC_2 and _3, since available in the driver

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I'm actually thinking about removing them, because there are so many different product lines, and different amount of ADCs they have, and also some ADCs share interrupt vector, so there should be some code for identifying which instance calls the interrupt. I would like another PR to do these things because this PR can be merged so users of STM32 can have basic ADC support.
But I'm worrying what Geo said about the merge window, but I see zephyr's doc says

As a general rule, if you miss the merge window for a given feature, the best thing to do is to wait for the next development cycle. (An occasional exception is made for drivers for previously unsupported hardware; if they do not touch any other in-tree code, they cannot cause regressions and should be safe to add at any time).

So if this passes all tests and clean, we should be able to merge this PR soon, right?

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This is up to @galak to settle on this. Though, I'm not quite in favor of it. Even it could not be a source of regression, it could be a source of bugs, and branch maturity is tightly controlled.
Besides, there are several PR that could pretend be merged as this PR (L1/G0/WB). There is no reason this one is privileged.
So I think the paragraph you mention should actually be corrected.

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Understand, so I'll just wait. ;)

endif # ADC_STM32