Add OpenTitan watchdog support #57501

tkng-rivos · 2023-05-02T23:57:56Z

The OpenTitan contains a HWIP called the Always-On (AON) Timer, which has two features - a wakeup timer and a watchdog timer. This patch series is concerned solely with the watchdog feature and does the following:

Adds the OpenTitan watchdog dts binding
Adds a driver for the watchdog
Adds the watchdog for the OpenTitan Earlgrey "board".

More details in the commits.

The AON Timer spec can be found here:
https://opentitan.org/book/hw/ip/aon_timer/index.html

To make the watchdog interrupt work with OpenTitan Earlgrey, some changes were needed to be made to the PLIC configuration.

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drivers/watchdog/wdt_opentitan.c

stale

drivers/watchdog/Kconfig.opentitan

drivers/watchdog/wdt_opentitan.c

tkng-rivos · 2023-05-09T05:20:39Z

I've made a few adjustments to the driver:

I added offset labels to the reg block struct. I would still prefer to have the reg block struct instead of going with an alternative.
I changed the logic surrounding how a timeout is chosen when the requested timeout values approach max_uint32. Before, I had simply returned an errored state when the requested max timeout was too large to fit in the hardware register. I added a check to see if it can fit in the requested [min, max] while respecting the bite timeout >= bark timeout requirement.
I originally had a lock attribute that would be set in the devicetree to indicate that the watchdog configuration would be "locked" by hardware, but removed it before the PR as I thought it wouldn't be so useful. Revisiting it, I added it back because I couldn't see a good way to give the user an option to adjust this setting.

drivers/watchdog/wdt_opentitan.c

tkng-rivos · 2023-05-10T01:59:05Z

I made a mistake when opening the PR in that I did not test it with the OpenTitan Verilator simulation; instead I used a QEMU setup I have locally. Lo and behold, it did not work with the Verilator simulation. I have investigated the cause and it seems like some additional configuration was needed to activate the watchdog reset functionality in the power management block.

Thus, I have included additional patches for adding a barebones devicetree binding for the power manager register block in the OpenTitan Earlgrey. All it has is a register configuration so that we can define the addresses of the necessary registers are; nothing else is implemented. These registers are used at SoC init to enable the watchdog reset. Note that the watchdog is not active until the watchdog timer itself is activated. Without these patches, the watchdog "bite" will never trigger a reset.

I have since tested the Verilator simulation and confirmed that both the bark and bite work with a modified version of the watchdog sample, which basically checks for the WDT_MULTISTAGE configuration option and adjusts the watchdog timeout installation with a 2-stage timeout. If interested, I can add that change to the patch series.

drivers/watchdog/wdt_opentitan.c

boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig

soc/riscv/riscv-privilege/opentitan/soc.c

tkng-rivos · 2023-05-22T17:51:03Z

Fixed some dead links in the OpenTitan Earlgrey page as well.

fkokosinski · 2023-05-25T08:15:41Z

@tkng-rivos could you rebase?

concerns addressed

carlescufi · 2023-05-25T14:16:11Z

@tkng-rivos please rebase and resolve conflicts

The OpenTitan AON Timer is a hardware device that has two features: the wakeup timer and watchdog timer. This commit series implements the watchdog feature. The spec can be found here: https://opentitan.org/book/hw/ip/aon_timer/index.html Signed-off-by: Tyler Ng <tkng@rivosinc.com>

The OpenTitan watchdog driver is a watchdog driver that can be configured with two stages: a watchdog "bark", which generates an interrupt, and a watchdog "bite", which resets the system. The two-stage watchdog can be enabled by setting CONFIG_WDT_MULTISTAGE=y. Otherwise, the driver functions as a single-stage watchdog. A callback function may be set for the bark interrupt through the wdt setup interface, but will only be used if the two-stage watchdog is enabled. It must be configured for the first watchdog stage. The driver controls only the watchdog portion of the OpenTitan AON timer. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

Adds the AON Timer device in the OpenTitan Earlgrey device tree. Adds overlay files to enable the watchdog and set the alias to `watchdog0`. Adds the AON timer (watchdog part) to the supported features section of the OpenTitan documentation. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

1. Fixes the number of interrupts in OpenTitan by default. This should be 32 + 185 = 217 IRQs, as there are 185 configurable registers, including interrupt 0. 2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a PLIC interrupt on IRQ 11. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

The OpenTitan power manager is responsible for changing the OpenTitan's operation to and from low power state. This patch adds a simple binding for the power manager's config registers. This is part of the OpenTitan watchdog patch series. The power manager HWIP block needs to be configured to enable the watchdog reset functionality in the OpenTitan Verilator simulation. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

Adds the pwrmgr devicetree node. This is a simple binding that holds only the address of the registers for now. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

Adds watchdog reset as a reset source at SoC init. This is achieved by: 1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog reset is enabled. 2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change. 3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the change has been processed. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Note that the timer itself is not enabled here, only the reset function. Signed-off-by: Tyler Ng <tkng@rivosinc.com>

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tkng-rivos requested review from nashif, galak, kgugala and pgielda as code owners May 2, 2023 23:57

zephyrbot added area: Watchdog Watchdog area: Devicetree Binding PR modifies or adds a Device Tree binding area: RISCV RISCV Architecture (32-bit & 64-bit) labels May 2, 2023

zephyrbot requested review from carlocaione, edersondisouza, fkokosinski, katsuster, martinjaeger, mgielda and tgorochowik May 2, 2023 23:58

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tkng-rivos force-pushed the dev/tkng/opentitan_wdt branch from d042e59 to f33cf0b Compare May 3, 2023 01:54

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tkng-rivos dismissed carlocaione’s stale review via 19dc71c May 19, 2023 20:25

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tkng-rivos dismissed stale reviews from carlocaione and fkokosinski via 29b6242 May 22, 2023 17:48

tkng-rivos force-pushed the dev/tkng/opentitan_wdt branch from bba6f72 to 29b6242 Compare May 22, 2023 17:48

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tkng-rivos added 7 commits May 25, 2023 10:52

tkng-rivos dismissed stale reviews from fkokosinski and carlocaione via db6531b May 25, 2023 17:54

tkng-rivos force-pushed the dev/tkng/opentitan_wdt branch from 29b6242 to db6531b Compare May 25, 2023 17:54

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nashif merged commit 28a18ec into zephyrproject-rtos:main May 26, 2023
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