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RFC: arch: arm: Remove aarch32 directory and split Cortex-M and Cortex-A/r code #60031
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fabiobaltieri
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zephyrproject-rtos:main
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SgrrZhf:topics/huizha01/split-cortex-m-and-cortex-ar
Sep 13, 2023
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87f757d
arch: arm: Remove aarch32 directory
SgrrZhf bb24e9a
include: arch: arm: Remove aarch32 directory
SgrrZhf fe5d8c7
arch: arm: cortex-m: Move irq_relay.S to the cortex-m directory
SgrrZhf 26597a3
arch: arm: Separate common swap code
SgrrZhf a034e86
arch: arm: Separate common irq_manage and isr_wrapper code
SgrrZhf e3b4244
arch: arm: Separate common exc header file
SgrrZhf 16d0e29
arch: arm: Separate common prep_c code
SgrrZhf 0b9cf13
arch: arm: Separate common thread code
SgrrZhf 67e8f39
arch: arm: Separate common cpu_idle codes
SgrrZhf 2aff843
arch: arm: Separate common kernel_arch_func code
SgrrZhf 61b0703
doc: release-notes: Add Aarch32 v3.5.0 notes
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,95 @@ | ||
| /* | ||
| * Copyright (c) 2013-2014 Wind River Systems, Inc. | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
|
|
||
| /** | ||
| * @file | ||
| * @brief ARM Cortex-A and Cortex-R power management | ||
| * | ||
| */ | ||
|
|
||
| #include <zephyr/toolchain.h> | ||
| #include <zephyr/linker/sections.h> | ||
|
|
||
| #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE) | ||
| #include <soc_cpu_idle.h> | ||
| #endif | ||
|
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| _ASM_FILE_PROLOGUE | ||
|
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| GTEXT(arch_cpu_idle) | ||
| GTEXT(arch_cpu_atomic_idle) | ||
|
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| .macro _sleep_if_allowed wait_instruction | ||
| #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) | ||
| push {r0, lr} | ||
| bl z_arm_on_enter_cpu_idle | ||
| /* Skip the wait instruction if on_enter_cpu_idle() returns false. */ | ||
| cmp r0, #0 | ||
| beq _skip_\@ | ||
| #endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ | ||
|
|
||
| /* | ||
| * Wait for all memory transactions to complete before entering low | ||
| * power state. | ||
| */ | ||
| dsb | ||
| \wait_instruction | ||
|
|
||
| #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE) | ||
| /* Inline the macro provided by SoC-specific code */ | ||
| SOC_ON_EXIT_CPU_IDLE | ||
| #endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */ | ||
|
|
||
| #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK) | ||
| _skip_\@: | ||
| pop {r0, lr} | ||
| #endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */ | ||
| .endm | ||
|
|
||
| SECTION_FUNC(TEXT, arch_cpu_idle) | ||
| #ifdef CONFIG_TRACING | ||
| push {r0, lr} | ||
| bl sys_trace_idle | ||
| pop {r0, lr} | ||
| #endif /* CONFIG_TRACING */ | ||
|
|
||
| /* Enter low power state */ | ||
| _sleep_if_allowed wfi | ||
|
|
||
| /* | ||
| * Clear PRIMASK and flush instruction buffer to immediately service | ||
| * the wake-up interrupt. | ||
| */ | ||
| cpsie i | ||
| isb | ||
|
|
||
| bx lr | ||
|
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||
| SECTION_FUNC(TEXT, arch_cpu_atomic_idle) | ||
| #ifdef CONFIG_TRACING | ||
| push {r0, lr} | ||
| bl sys_trace_idle | ||
| pop {r0, lr} | ||
| #endif /* CONFIG_TRACING */ | ||
|
|
||
| /* | ||
| * Lock PRIMASK while sleeping: wfe will still get interrupted by | ||
| * incoming interrupts but the CPU will not service them right away. | ||
| */ | ||
| cpsid i | ||
|
|
||
| /* r0: interrupt mask from caller */ | ||
|
|
||
| /* No BASEPRI, call wfe directly | ||
| */ | ||
| _sleep_if_allowed wfe | ||
|
|
||
| cmp r0, #0 | ||
| bne _irq_disabled | ||
| cpsie i | ||
| _irq_disabled: | ||
|
|
||
| bx lr |
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This should probably be updated to
@SgrrZhf @povergoing @microbuilderSince Ioannis is no longer involved with the project.There was a problem hiding this comment.
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Sorry, ignore this and lets make a separate PR since there are a lot of instances of this, and I agree with @carlocaione ... lets separate M and A/R here, and nothing else. I'll make a PR to cleanup
CODEOWNERSlater.There was a problem hiding this comment.
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Updating the CODEOWNERS might also be a chance to officially blame me for the MMU stuff for everyone to see...