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STM32F4x power management #65050

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merged 2 commits into from Nov 21, 2023
Merged

STM32F4x power management #65050

merged 2 commits into from Nov 21, 2023

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niedzwiecki-dawid
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@niedzwiecki-dawid niedzwiecki-dawid commented Nov 10, 2023 •
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Add Power Management support for the STM32F4x chips

ceolin
ceolin previously approved these changes Nov 11, 2023
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Minor comment, it looks good from the subsystem usage perspective.

erwango
erwango requested changes Nov 13, 2023
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Few changes requested, but otherwise looks good.

This being said, would you mind enabling board on samples/boards/stm32/power_mgmt/blinky ?

I'm having a try and I can't see the LED blinking nor I can see power savings.
I'm using nucleo_f429zi and measuring power on JP5. Please let me know if this should be made in a different way.

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erwango commented Nov 13, 2023

Note:
I can see different behavior with CONFIG_DEBUG=y and =n

CONFIG_DEBUG=y:

  • LED is blinking (10 sec in stead of 2 sec)
  • Power is around 5mA

CONFIG_DEBUG=n:

  • LED is not blinking
  • Power is around 55mA

Difference between the 2 configs should be DBGMCU_CR_DBG_SLEEP value in DBGMCU->CR

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Sure, I'll check the blinky sample.

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I've reproduced the same problem. It is about the stack size. Using the RTC as idle timer requires IDLE_STACK_SIZE at least 500, because of additional calls to set the alarm. With that, everything works fine on my side. Power is ~6,9mA regardless of the CONFIG_DEBUG.

Now, I'm thinking if I should add increasing the idle stack automatically or let the user do it in the config files. I would rather chose the second option with some additional documentation somewhere.

@zephyrbot zephyrbot added the area: Samples Samples label Nov 15, 2023
@niedzwiecki-dawid
pm: add power management for stm32f4x
d63e9e7 
Add soc power management for the STM32F4x chips.

One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.

The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.

The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
@niedzwiecki-dawid
tests: pm: add soc pm tests and sample for stm32f4x chip
a7e76ff 
Add soc power management test and blinky sample for the nucleo_f429zi
board.

Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
@erwango erwango requested a review from ceolin November 16, 2023 12:59
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@ceolin ping

@fabiobaltieri fabiobaltieri merged commit e6c7a4c into zephyrproject-rtos:main Nov 21, 2023
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@niedzwiecki-dawid niedzwiecki-dawid mentioned this pull request Nov 24, 2023
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@ceolin ceolin ceolin approved these changes

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