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soc: arm: st_stm32: add support for STM32H7B0 SoC #65092

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merged 3 commits into from
Nov 15, 2023
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soc: arm: st_stm32: add support for STM32H7B0 SoC #65092

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a2f166b
soc: arm: st_stm32: add support for stm32h7b0xx and stm32h7b0xxQ
CharlesDias Nov 11, 2023
c8190da
drivers: clock_control: define clock freq for STM32H7B0
CharlesDias Nov 12, 2023
b4a8a0b
dts: arm: st: h7: add support for stm32h7b0
CharlesDias Nov 12, 2023
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2 changes: 2 additions & 0 deletions drivers/clock_control/clock_stm32_ll_h7.c
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Original file line number Diff line number Diff line change
Expand Up @@ -107,6 +107,7 @@
#define AHB_FREQ_MAX 275000000UL
#define APBx_FREQ_MAX 137500000UL
#elif defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) ||\
defined(CONFIG_SOC_STM32H7B0XX) || defined(CONFIG_SOC_STM32H7B0XXQ) ||\
defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
#define SYSCLK_FREQ_MAX 280000000UL
#define AHB_FREQ_MAX 280000000UL
Expand Down Expand Up @@ -829,6 +830,7 @@ int stm32_clock_control_init(const struct device *dev)

/* HW semaphore Clock enable */
#if defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) || \
defined(CONFIG_SOC_STM32H7B0XX) || defined(CONFIG_SOC_STM32H7B0XXQ) || \
defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_HSEM);
#else
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27 changes: 27 additions & 0 deletions dts/arm/st/h7/stm32h7b0.dtsi
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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2023 Charles Dias <charlesdias.cd@outlook.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <st/h7/stm32h7a3.dtsi>

/*
* STM32H7B0 line contains the same peripherals as STM32H7A3,
* with addition of CRYPTO/HASH and OTFDEC peripherals.
*/
/ {
soc {
compatible = "st,stm32h7b0", "st,stm32h7", "simple-bus";

cryp: cryp@48021000 {
compatible = "st,stm32-cryp";
reg = <0x48021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
interrupt-names = "cryp";
status = "disabled";
};
};
};
17 changes: 17 additions & 0 deletions dts/arm/st/h7/stm32h7b0Xb.dtsi
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@@ -0,0 +1,17 @@
/*
* Copyright (c) 2023 Charles Dias <charlesdias.cd@outlook.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <st/h7/stm32h7b0.dtsi>
/ {
soc {
flash-controller@52002000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
14 changes: 2 additions & 12 deletions dts/arm/st/h7/stm32h7b3.dtsi
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Expand Up @@ -5,23 +5,13 @@
*/

#include <mem.h>
#include <st/h7/stm32h7a3.dtsi>
#include <st/h7/stm32h7b0.dtsi>

/*
* STM32H7B3 line contains the same peripherals as STM32H7A3,
* with addition of CRYPTO/HASH and OTFDEC peripherals
* STM32H7B3 line contains the same peripherals as STM32H7B0.
*/
/ {
soc {
compatible = "st,stm32h7b3", "st,stm32h7", "simple-bus";

cryp: cryp@48021000 {
compatible = "st,stm32-cryp";
reg = <0x48021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
interrupt-names = "cryp";
status = "disabled";
};
};
};
15 changes: 15 additions & 0 deletions soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx
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@@ -0,0 +1,15 @@
# ST STM32H7B0XX MCU configuration options

# Copyright (c) 2023 Charles Dias <charlesdias.cd@outlook.com>
# SPDX-License-Identifier: Apache-2.0

if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ

config SOC
default "stm32h7b0xxQ" if SOC_STM32H7B0XXQ
default "stm32h7b0xx" if SOC_STM32H7B0XX

config NUM_IRQS
default 155

endif # SOC_STM32H7B0XX || SOC_STM32H7B0XXQ
10 changes: 10 additions & 0 deletions soc/arm/st_stm32/stm32h7/Kconfig.soc
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Expand Up @@ -73,6 +73,16 @@ config SOC_STM32H7A3XXQ
select CPU_CORTEX_M7
select CPU_HAS_FPU_DOUBLE_PRECISION

config SOC_STM32H7B0XX
bool "STM32H7B0XX"
select CPU_CORTEX_M7
select CPU_HAS_FPU_DOUBLE_PRECISION

config SOC_STM32H7B0XXQ
bool "STM32H7B0XXQ"
select CPU_CORTEX_M7
select CPU_HAS_FPU_DOUBLE_PRECISION

config SOC_STM32H7B3XX
bool "STM32H7B3XX"
select CPU_CORTEX_M7
Expand Down
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