[RFC] risc-v: drivers: intc_plic: enabled interrupts to be handled by all cores #65922
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| uint32_t en_value; | ||
| uint32_t key; |
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these 2 line changes are probably not necessary
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I think it would be important for @luchnikov to review as well. |
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Ugh... @con-pax - may need to rebase and resolve conflicts. |
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@cfriedt rebased and pushed. |
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@ycsin - can you do a bisect on the test that's failing? I would guess it's probably from one of the ones that were just merged ahead of this. |
@cfriedt Hey Chris, apologies, this was my bad: I see something that in my haste, my rebase wasn't successful: I will rebase again from the point of previous approvals |
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The plic uses contexts to seperate irq enables, threshold priority and claim complete registers from each core for a given platform. As well as this, each privilege level has its own context. for multi-core platform's, we need to be able to enable/ disable a global interrupt for all the cores that are associated with Zephyr. To do this, we need to make some assumptions: 1. The privilege contexts are contiguous 2. M mode context is first, followed by S mode. We know how many cpus are used in an application and each cpu's hartid, thanks to some very handy inline functions. So we iterate through each cpu and use the hartid of a cpu in the calculation of the context. While we are at it, In an effort to make the driver more readable, allign with the macro naming convention outlined in Linux's PLIC driver Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
The plic has a very simple mechanism to claim an interrupt as well as to complete and clear it. The same register is read from/ written to to achieve this. Get the ID of the HART that serviced the interrupt and write to the claim complete register in the correct context Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
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Hey @ycsin @fkokosinski |
This patch set is to fix an issue #65489.
The problem to fix is that the first context of the PLIC was hardcoded into the driver. The side effect of that was to disable other cores in a multi-core complex from handling interrupts.
The solution presented here started off life as a cut and past from what is done in Linux, however A slightly more elegant solution raised its head during the process: basically, We know how many CPU's will be associated with a Zephyr application prior to compile time. Also, if its an SMP set up we have a mapping of the hartid to the cpu right from the start.
We can leverage this list of CPU's to enable only the contexts of the harts that are required to run in Zephyr, allowing Zephyr to also play nicely in an AMP setup.