STM32 Add PM Suspend to Ram support #67534
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zephyrbot
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area: GPIO
area: ADC
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teburd
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erwango
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drivers/adc/adc_stm32.c
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| pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, | ||
| PM_ALL_SUBSTATES); | ||
| pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, | ||
| PM_ALL_SUBSTATES); |
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@ceolin Shouldn't preventing to go in one state also preventing to go in a deeper state ?
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Nope, it just excludes the given state / substate. If the next scheduled event is enough for a deeper state be used, this will happen.
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@ceolin I understand this opens to more cases, but are there possible cases were a subsystem can work in one state but can work in a deeper state ?
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Remove initialization of static variable to 0 to prevent resetting the value when reinitializing the driver after resume from standby. This has no impact since static variables are initialized to 0 by default. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for a backup standby timer in STM32 LPTIM driver for cases when the LPTIM is not available (ie standby low power mode). A counter (typically RTC) is used for such a case. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix a bug where after a standby, it was impossible to reenable a GPIO clock. A counter is incremented each time pm_device_runtime_get is called, and decremented each time pm_device_runtime_put is called. The clock is only enabled if this counter equals 1. When configuring a GPIO (as input or output), the timer is incremented, and when disconnecting it, it is both incremented and decremented. Thus the next time we try to configuring it, the clock is not enabled (since the counter will now be equal to 2). This causes a problem when using low power standby mode: after wakeup all clocks are disabled and the GPIO clock can not be reenabled. This commit fixes this bug by not incrementing the counter when disconnect is asked (or in other words incrementing it only when configuring either an input or an output). Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
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…ress Prevent the system to enter Suspend to RAM state while UART operation is in progress. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When resuming from low power mode, if UART is disabled, this means that we come from a mode that reset the registers, so we redo a full init of the driver. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Prevents the system to go in Suspend to RAM low power mode while ADC measurement is in progress. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
…gress Prevent the system to enter Suspend to RAM state while RNG operation is in progress. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
With PM, when resuming from low power mode, reenable the RNG register clocks and check the health register. If it is not set to the desired value, it means we exit Suspend to RAM mode, and that the RNG needs to be reinitialized. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
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erwango
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FRASTM
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This PR adds generic support for Suspend to RAM PM mode.
To that end, we use STM32 Standby mode with RAM retention (for SoC that provide it).
In low power applications, the Systick is typically given by a LPTIM. Since LPTIM is not clocked in Standby mode, before switching to this mode, we activate another clock (typically RTC) that works in Standby to play the role of Systick.
This was heavily influenced by the work in #63187 (Many thanks!).
A few peripherals (GPIO, ADC, Serial and entropy) have also been adapted to be compatible with this mode.
This other PR #67536 demonstrates the functionality on the STM32WBA series.