risc-v: add Microchip's PolarFire SoC FPGA manager interface #67802
Conversation
zephyrbot
added
area: RISCV
zephyrbot
requested review from
albertofloyd,
carlocaione,
cfriedt,
edersondisouza,
fkokosinski,
galak,
jvasanth1,
katsuster,
kgugala,
mgielda,
msierszulski,
npitre,
tgorochowik and
VenkatKotakonda
dts/riscv/microchip/mpfs.dtsi
Outdated
| compatible = "microchip,mpfs-fpga"; | ||
| status = "disabled"; |
There was a problem hiding this comment.
Nitpick: this indentation looks wrong
There was a problem hiding this comment.
@fkokosinski a fix has been implemented
drivers/fpga/fpga_mpfs.c
Outdated
| #define MSS_SCBMAILBOX ((volatile uint32_t *)(0x37020800UL)) | ||
| #define MSS_SCB_SERVICES_CR (*(volatile uint32_t *)(0x37020050UL)) | ||
| #define MSS_SCB_SERVICES_SR (*(volatile uint32_t *)(0x37020054UL)) |
There was a problem hiding this comment.
IMO we should be reading these addresses from the device tree. Maybe a syscon node/driver would be a good fit here?
There was a problem hiding this comment.
I agree. We will look at this, thanks!
There was a problem hiding this comment.
@carlocaione @fkokosinski
Thanks for this one guys, we have went with a different approach
drivers/fpga/fpga_mpfs.c
Outdated
| #define MSS_SCB_SERVICES_SR (*(volatile uint32_t *)(0x37020054UL)) | ||
|
|
||
| #define SCBCTRL_SERVICESCR_REQ (0u) | ||
| #define SCBCTRL_SERVICESCR_REQ_MASK (1u << SCBCTRL_SERVICESCR_REQ) |
There was a problem hiding this comment.
| #define SCBCTRL_SERVICESCR_REQ_MASK (1u << SCBCTRL_SERVICESCR_REQ) | |
| #define SCBCTRL_SERVICESCR_REQ_MASK BIT(SCBCTRL_SERVICESCR_REQ) |
There was a problem hiding this comment.
@fkokosinski thanks! we will fix this
drivers/fpga/fpga_mpfs.c
Outdated
| #define SCBCTRL_SERVICESCR_REQ_MASK (1u << SCBCTRL_SERVICESCR_REQ) | ||
|
|
||
| #define SCBCTRL_SERVICESSR_BUSY (1u) | ||
| #define SCBCTRL_SERVICESSR_BUSY_MASK (1u << SCBCTRL_SERVICESSR_BUSY) |
There was a problem hiding this comment.
| #define SCBCTRL_SERVICESSR_BUSY_MASK (1u << SCBCTRL_SERVICESSR_BUSY) | |
| #define SCBCTRL_SERVICESSR_BUSY_MASK BIT(SCBCTRL_SERVICESSR_BUSY) |
There was a problem hiding this comment.
@fkokosinski thanks! we will fix this one too
drivers/fpga/fpga_mpfs.c
Outdated
| #define SCBCTRL_SERVICESSR_BUSY_MASK (1u << SCBCTRL_SERVICESSR_BUSY) | ||
|
|
||
| #define SCBCTRL_SERVICESSR_STATUS (16u) | ||
| #define SCBCTRL_SERVICESSR_STATUS_MASK (0xFFFFu << SCBCTRL_SERVICESSR_STATUS) |
There was a problem hiding this comment.
| #define SCBCTRL_SERVICESSR_STATUS_MASK (0xFFFFu << SCBCTRL_SERVICESSR_STATUS) | |
| #define SCBCTRL_SERVICESSR_STATUS_MASK GENMASK(SCBCTRL_SERVICESSR_STATUS + 3, SCBCTRL_SERVICESSR_STATUS) |
There was a problem hiding this comment.
@fkokosinski, excellent, thanks for the pointing out that macro
con-pax
force-pushed
the
mpfs_icicle-fpga_manager
branch
from
540f8e8
to
ce41ef4
Compare
Hey @cfriedt, |
|
I will go fix the conflicts on this now 😃 |
con-pax
force-pushed
the
mpfs_icicle-fpga_manager
branch
from
ce41ef4
to
86f548c
Compare
Add support for Microchip's PolarFire SoC system controller QSPI interface. Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
Add Microchip's PolarFire SoC mailbox node. Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
Add FPGA driver support for Microchip PolarFire SoC. Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
Microchip's PolarFire SoC interface with on-board spi nor flash via system controller. This on-board spi nor flash can be used to store FPGA design bitstream's. Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
|
@fkokosinski, @kgugala - can either of you add a +1 after this was rebased to fix merge conflicts? |
|
@cfriedt done :) |
This patch set adds support for the "Auto Update" feature on PolarFire SoC that allows for writing an FPGA bitstream to the SPI flash connected to the system controller.
On power cycle, "Auto Update" will take place, and program the FPGA with the contents of the SPI flash - provided that that image is valid and an actual upgrade from that already programmed.
An important note: this service is not possible on PolarFire SoC engineering sample's, due to a bug on the QSPI controller connected to the system controller.