-
Notifications
You must be signed in to change notification settings - Fork 6.2k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
hwmv2: convert SiFive and RISC-V QEMU boards #68925
hwmv2: convert SiFive and RISC-V QEMU boards #68925
Conversation
6b3ec05
to
ddc8a23
Compare
ddc8a23
to
63affb6
Compare
Ha, just as I had finished porting hifive1 and revb! |
46a37ce
to
f2bf770
Compare
Hi @nordicjm, I've addressed you comments. PTAL :) |
5c0b0f6
to
abca206
Compare
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Minor nit.
abca206
to
2f4289a
Compare
Hi @nordicjm, I've addressed your 2nd round of comments. PTAL |
Looks good, thanks, should hear back about the privileged riscv part tomorrow |
2f4289a
to
e708642
Compare
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
update docs/maintainers as needed
Rebase needed |
e708642
to
e1f5b7b
Compare
ed56b07
to
853b16b
Compare
select SOC_FAMILY_SIFIVE_FREEDOM | ||
|
||
config SOC_SERIES | ||
default "e300" if SOC_SERIES_SIFIVE_FREEDOM_E300 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
We could expand the e300
to be more verbose and include the SoC family name, i.e. sifive_freedom_e300
(with vendor) or freedom_e300
(without vendor).
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
It's a future thing, e300 is fine for now but yes in future might have to expand it
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
It's a future thing, e300 is fine for now but yes in future might have to expand it
I think current proposal is fine.
If we're later going to use those values internally, like we do the the CONFIG_SOC
, then we should be generating those.
Just like we do for boards.
But there are a couple of reasons this is not done in first iteration of hwmv2, so let's not worry to much now.
But thanks for raising awareness on this @nordicjm 👍
select CPU_HAS_FPU | ||
select RISCV_ISA_RV32I | ||
select RISCV_ISA_EXT_ZICSR | ||
select RISCV_ISA_EXT_ZIFENCEI |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I don't have a strong preference on this. But if we go ahead and convert them to a single board with variants, I suppose that qemu_virt_riscv32e
should also be included in the process?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
initial feeling is that it's the SoC which is either 32 bit or 64bit, and thus you select the SoC of the arch you want.
Thus the board indirectly select 32 / 64 bit based on the SoC it selects.
Not the board which should directly select 32 or 64 bit.
853b16b
to
2cc432b
Compare
Btw. our runners seem to be experiencing some problems:
I'll wait a bit before restarting the workflow to not flood the whole thing with more workload while it's not responding. |
OK, the CI now only reports one error that looks unrelated to this PR:
|
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Also rebase will fix the test failure
This commit adds support for the SiFive Freedom E310 SoC for the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive1 board (`hifive1` target) to the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive1 Rev. B board (`hifive1_revb` target) to the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds support for the SiFive Freedom U540 SoC for the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive Unleashed board (`hifive_unleashed` target) to the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds support for the SiFive Freedom U740 SoC for the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive Unmatched board (`hifive_unmatched` target) to the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SparkFun RED-V Things Plus board (`sparkfun_red_v_things_plus` target) to the Zephyr Hardware Model v2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the virt SoC (generic virt machine) to the Zephyr HWMv2. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RISCV-V 32 bit board to Zephyr HWMvW. This includes the following former targets: * qemu_riscv32 * qemu_riscv32_smp * qemu_riscv32_xip Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RV32E board to Zephyr HWMvW. This includes the following former target: qemu_riscv32e. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RISCV-V 64 bit board to Zephyr HWMvW. This includes the following former targets: * qemu_riscv64 * qemu_riscv64_smp Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit updates the paths assigned to the RISC-V area of maintenance to include targets based on the SiFive Freedom SoC family. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2cc432b
to
09ac2ee
Compare
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thanks for port!
Targets in question:
hifive1
hifive1_revb
hifive_unleashed
hifive_unmatched
qemu_riscv32_xip
sparkfun_red_v_things_plus
Converted to:
Edit:
I see that two targets also use SoCs from the FE300 SoC series:Done.qemu_riscv32_xip
andsparkfun_red_v_things_plus
. I'll start porting them right away.