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hwmv2: convert SiFive and RISC-V QEMU boards #68925

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merged 13 commits into from
Feb 23, 2024

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@fkokosinski fkokosinski commented Feb 13, 2024

Targets in question:

  • hifive1
  • hifive1_revb
  • hifive_unleashed
  • hifive_unmatched
  • qemu_riscv32_xip
  • sparkfun_red_v_things_plus

Converted to:

west build -p -b hifive1 samples/hello_world -t run
west build -p -b hifive1@B samples/hello_world -t run
west build -p -b hifive_unleashed samples/hello_world -t run
west build -p -b hifive_unmatched samples/hello_world -t run
west build -p -b sparkfun_red_v_things_plus samples/hello_world
west build -p -b qemu_riscv32/fe310/xip  samples/hello_world -t run

Edit:
I see that two targets also use SoCs from the FE300 SoC series: qemu_riscv32_xip and sparkfun_red_v_things_plus. I'll start porting them right away. Done.

@fkokosinski fkokosinski marked this pull request as ready for review February 13, 2024 10:44
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Ha, just as I had finished porting hifive1 and revb!

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@fkokosinski fkokosinski force-pushed the 54871-hwmv2-sifive branch 2 times, most recently from 46a37ce to f2bf770 Compare February 13, 2024 13:02
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Hi @nordicjm, I've addressed you comments. PTAL :)

@fkokosinski fkokosinski force-pushed the 54871-hwmv2-sifive branch 2 times, most recently from 5c0b0f6 to abca206 Compare February 13, 2024 13:17
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Minor nit.

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Hi @nordicjm, I've addressed your 2nd round of comments. PTAL

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Looks good, thanks, should hear back about the privileged riscv part tomorrow

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update docs/maintainers as needed

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Rebase needed

@zephyrbot zephyrbot added area: RISCV RISCV Architecture (32-bit & 64-bit) area: mcumgr labels Feb 21, 2024
@fkokosinski fkokosinski force-pushed the 54871-hwmv2-sifive branch 5 times, most recently from ed56b07 to 853b16b Compare February 22, 2024 10:40
select SOC_FAMILY_SIFIVE_FREEDOM

config SOC_SERIES
default "e300" if SOC_SERIES_SIFIVE_FREEDOM_E300
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We are planning to have the value and name of this linked in future: #69317
But this raises an interesting issue @tejlmand because if just "e300" is used, that's so generic it's bound to have a name clash in future

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We could expand the e300 to be more verbose and include the SoC family name, i.e. sifive_freedom_e300 (with vendor) or freedom_e300 (without vendor).

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It's a future thing, e300 is fine for now but yes in future might have to expand it

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It's a future thing, e300 is fine for now but yes in future might have to expand it

I think current proposal is fine.
If we're later going to use those values internally, like we do the the CONFIG_SOC, then we should be generating those.
Just like we do for boards.

But there are a couple of reasons this is not done in first iteration of hwmv2, so let's not worry to much now.
But thanks for raising awareness on this @nordicjm 👍

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select CPU_HAS_FPU
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
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qemu_virt_riscv32 and qemu_virt_riscv64 should probably become one board and use variant to specify which one is being built where no variant = 32-bit and variant "64" = 64-bit, thoughts @gmarull @aescolar ?

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I don't have a strong preference on this. But if we go ahead and convert them to a single board with variants, I suppose that qemu_virt_riscv32e should also be included in the process?

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initial feeling is that it's the SoC which is either 32 bit or 64bit, and thus you select the SoC of the arch you want.
Thus the board indirectly select 32 / 64 bit based on the SoC it selects.

Not the board which should directly select 32 or 64 bit.

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fkokosinski commented Feb 22, 2024

Btw. our runners seem to be experiencing some problems:

The self-hosted runner: zephyr-runner-linux-x64-4xlarge-deployment-g2tcl-lwwnp lost communication with the server. Verify the machine is running and has a healthy network connection. Anything in your workflow that terminates the runner process, starves it for CPU/Memory, or blocks its network access can cause this error.

I'll wait a bit before restarting the workflow to not flood the whole thing with more workload while it's not responding.

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OK, the CI now only reports one error that looks unrelated to this PR:

tests/subsys/mgmt/mcumgr/os_mgmt_info/mgmt.mcumgr.os.info.bt (nrf9160dk/nrf52840:tests/subsys/mgmt/mcumgr/os_mgmt_info/mgmt.mcumgr.os.info.bt) with error

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Also rebase will fix the test failure

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This commit adds support for the SiFive Freedom E310 SoC for the Zephyr
Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive1 board (`hifive1` target) to the
Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive1 Rev. B board (`hifive1_revb`
target) to the Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds support for the SiFive Freedom U540 SoC for the Zephyr
Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive Unleashed board (`hifive_unleashed`
target) to the Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds support for the SiFive Freedom U740 SoC for the Zephyr
Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SiFive HiFive Unmatched board (`hifive_unmatched`
target) to the Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the SparkFun RED-V Things Plus board
(`sparkfun_red_v_things_plus` target) to the Zephyr Hardware Model v2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the virt SoC (generic virt machine) to the Zephyr
HWMv2.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RISCV-V 32 bit board to Zephyr HWMvW. This
includes the following former targets:
* qemu_riscv32
* qemu_riscv32_smp
* qemu_riscv32_xip

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RV32E board to Zephyr HWMvW. This includes
the following former target: qemu_riscv32e.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit converts the QEMU RISCV-V 64 bit board to Zephyr HWMvW. This
includes the following former targets:
* qemu_riscv64
* qemu_riscv64_smp

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit updates the paths assigned to the RISC-V area of maintenance to
include targets based on the SiFive Freedom SoC family.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
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Thanks for port!

@nordicjm nordicjm merged commit eba99f7 into zephyrproject-rtos:collab-hwm Feb 23, 2024
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@fkokosinski fkokosinski deleted the 54871-hwmv2-sifive branch February 23, 2024 12:15
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6 participants