boards: nxp: rd_rw612_bga: enable DMA

boards/nxp/rd_rw612_bga/doc/index.rst

@@ -39,6 +39,8 @@ Supported Features
 +-----------+------------+-----------------------------------+
 | USART     | on-chip    | serial                            |
 +-----------+------------+-----------------------------------+
+| DMA       | on-chip    | dma                               |
++-----------+------------+-----------------------------------+
 | SPI       | on-chip    | spi                               |
 +-----------+------------+-----------------------------------+
 

boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi

@@ -100,3 +100,7 @@ arduino_spi: &flexcomm0 {
 		};
 	};
 };
+
+&dma0 {
+	status = "okay";
+};

boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml

@@ -15,5 +15,6 @@ toolchain:
 ram: 960
 flash: 65536
 supported:
+  - dma
   - gpio
   - spi

drivers/dma/dma_mcux_lpc.c

@@ -114,6 +114,28 @@ static void dma_mcux_lpc_irq_handler(const struct device *dev)
 #endif
 }
 
+#ifdef CONFIG_SOC_SERIES_RW6XX
+static inline void rw6xx_dma_addr_fixup(struct dma_block_config *block)
+{
+	/* RW6xx AHB design does not route DMA engine through FlexSPI CACHE.
+	 * Therefore, to use DMA from the FlexSPI space we must adjust the
+	 * source address to use the non cached FlexSPI region.
+	 * FlexSPI cached region is at 0x800_0000 (nonsecure) or 0x1800_0000
+	 * (secure). We move the address into non cached region, which is at
+	 * 0x4800_0000 or 0x5800_000.
+	 */
+	if (((block->source_address & 0xF8000000) == 0x18000000) ||
+	  ((block->source_address & 0xF8000000) == 0x8000000)) {
+		block->source_address = block->source_address + 0x40000000;
+	}
+	if (((block->dest_address & 0xF8000000) == 0x18000000) ||
+	  ((block->dest_address & 0xF8000000) == 0x8000000)) {
+		block->dest_address = block->dest_address + 0x40000000;
+	}
+
+}
+#endif
+
 static int dma_mcux_lpc_queue_descriptors(struct channel_data *data,
 					   struct dma_block_config *block,
 					   uint8_t src_inc,
@@ -228,6 +250,9 @@ static int dma_mcux_lpc_queue_descriptors(struct channel_data *data,
 					dest_inc,
 					MIN(local_block.block_size, max_xfer_bytes));
 
+#ifdef CONFIG_SOC_SERIES_RW6XX
+		rw6xx_dma_addr_fixup(&local_block);
+#endif
 		DMA_SetupDescriptor(data->curr_descriptor,
 				xfer_config,
 				(void *)local_block.source_address,
@@ -271,6 +296,9 @@ static int dma_mcux_lpc_queue_descriptors(struct channel_data *data,
 					MIN(local_block.block_size, max_xfer_bytes));
 		/* Mark this as invalid */
 		xfer_config &= ~DMA_CHANNEL_XFERCFG_CFGVALID_MASK;
+#ifdef CONFIG_SOC_SERIES_RW6XX
+		rw6xx_dma_addr_fixup(&local_block);
+#endif
 		DMA_SetupDescriptor(data->curr_descriptor,
 				xfer_config,
 				(void *)local_block.source_address,
@@ -586,6 +614,10 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel,
 	assert(block_config->source_address == ROUND_UP(block_config->source_address, width));
 	assert(block_config->dest_address == ROUND_UP(block_config->dest_address, width));
 
+#ifdef CONFIG_SOC_SERIES_RW6XX
+	rw6xx_dma_addr_fixup(block_config);
+#endif
+
 	DMA_SubmitChannelTransferParameter(p_handle,
 					xfer_config,
 					(void *)block_config->source_address,

dts/arm/nxp/nxp_rw6xx_common.dtsi

@@ -145,6 +145,15 @@
 		num-lines = <8>;
 		num-inputs = <64>;
 	};
+
+	dma0: dma-controller@104000 {
+		compatible = "nxp,lpc-dma";
+		reg = <0x104000 0x1000>;
+		interrupts = <1 0>;
+		status = "disabled";
+		#dma-cells = <1>;
+		dma-channels = <33>;
+	};
 };
 
 &flexspi {

tests/drivers/dma/loop_transfer/boards/rd_rw612_bga.overlay

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };