hwinfo: RW soc driver

boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi

@@ -136,3 +136,9 @@ arduino_i2c: &flexcomm2 {
 &ctimer0 {
 	status = "okay";
 };
+
+&pmu {
+	reset-causes-en = <PMU_RESET_CM33_LOCKUP>,
+			  <PMU_RESET_ITRC>,
+			  <PMU_RESET_AP_RESET>;
+};

boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml

@@ -22,3 +22,4 @@ supported:
   - entropy
   - watchdog
   - counter
+  - hwinfo

drivers/hwinfo/CMakeLists.txt

@@ -28,3 +28,4 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM4L       hwinfo_sam4l.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SMARTBOND   hwinfo_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_STM32       hwinfo_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_ANDES       hwinfo_andes.c)
+zephyr_library_sources_ifdef(CONFIG_HWINFO_RW61X       hwinfo_rw61x.c)

drivers/hwinfo/Kconfig

@@ -192,4 +192,11 @@ config HWINFO_ANDES
 	help
 	  Enable Andes hwinfo driver
 
+config HWINFO_RW61X
+	bool "RW61X hwinfo"
+	default y
+	depends on SOC_SERIES_RW6XX
+	help
+	  Enable RW61X hwinfo driver
+
 endif

drivers/hwinfo/hwinfo_rw61x.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/hwinfo.h>
+
+#include <fsl_ocotp.h>
+#include <fsl_power.h>
+
+/* Because of the ROM clearing the reset register and using scratch register
+ * which cannot be cleared, we have to "fake" this to meet the hwinfo api.
+ * Technically all the reset causes are already cleared by the ROM, but we will
+ * still clear them ourselves on the first call to clear them by user.
+ */
+static bool reset_cleared;
+
+ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
+{
+	uint32_t id_length = length;
+
+	if (OCOTP_ReadUniqueID(buffer, &id_length)) {
+		return -EINVAL;
+	}
+
+	return (ssize_t)id_length;
+}
+
+int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
+{
+	*supported = (
+		RESET_SOFTWARE		|
+		RESET_CPU_LOCKUP	|
+		RESET_WATCHDOG		|
+		RESET_SECURITY		|
+		RESET_DEBUG		|
+		RESET_HARDWARE
+	);
+
+	return 0;
+}
+
+int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
+{
+	if (reset_cleared) {
+		*cause = 0;
+		return 0;
+	}
+
+	uint32_t reset_cause = POWER_GetResetCause();
+
+	switch (reset_cause) {
+	case kPOWER_ResetCauseSysResetReq:
+		*cause = RESET_SOFTWARE;
+		break;
+	case kPOWER_ResetCauseLockup:
+		*cause = RESET_CPU_LOCKUP;
+		break;
+	case kPOWER_ResetCauseWdt:
+		*cause = RESET_WATCHDOG;
+		break;
+	case kPOWER_ResetCauseApResetReq:
+		*cause = RESET_DEBUG;
+		break;
+	case kPOWER_ResetCauseCodeWdt:
+	case kPOWER_ResetCauseItrc:
+		*cause = RESET_SECURITY;
+		break;
+	case kPOWER_ResetCauseResetB:
+		*cause = RESET_HARDWARE;
+		break;
+	default:
+		*cause = 0;
+		break;
+	}
+
+	return 0;
+}
+
+int z_impl_hwinfo_clear_reset_cause(void)
+{
+	POWER_ClearResetCause(kPOWER_ResetCauseAll);
+
+	reset_cleared = true;
+
+	return 0;
+}

dts/arm/nxp/nxp_rw6xx_common.dtsi

@@ -8,6 +8,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 #include <dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
 
 / {
 	chosen {
@@ -69,6 +70,11 @@
 		#clock-cells = <1>;
 	};
 
+	pmu: pmu@31000 {
+		reg = <0x31000 0x130>;
+		compatible = "nxp,rw-pmu";
+	};
+
 	trng: random@14000 {
 		compatible = "nxp,kinetis-trng";
 		reg = <0x14000 0x1000>;

dts/bindings/power/nxp,rw-pmu.yaml

@@ -0,0 +1,14 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP RW PMU
+
+compatible: "nxp,rw-pmu"
+
+include: base.yaml
+
+properties:
+  reset-causes-en:
+    type: array
+    description: |
+      List reset causes to enable, using bitmasks of SYS_RESET registers.

include/zephyr/dt-bindings/power/nxp_rw_pmu.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_
+
+#define PMU_RESET_CM33_SOFT_RESET 0x1
+#define PMU_RESET_CM33_LOCKUP 0x2
+#define PMU_RESET_WATCHDOG 0x4
+#define PMU_RESET_AP_RESET 0x8
+#define PMU_RESET_CODE_WATCHDOG 0x10
+#define PMU_RESET_ITRC 0x20
+#define PMU_RESET_RESETB 0x40
+#define PMU_RESET_ALL 0x7F
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ */

soc/nxp/rw/soc.c

@@ -10,6 +10,7 @@
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/linker/sections.h>
+#include <zephyr/sys/util_macro.h>
 
 #include <cortex_m/exception.h>
 #include <fsl_power.h>
@@ -246,6 +247,17 @@ static int nxp_rw600_init(void)
 	POWER_EnableResetSource(kPOWER_ResetSourceWdt);
 #endif
 
+#define PMU_RESET_CAUSES_ \
+	DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(pmu), reset_causes_en, DT_PROP_BY_IDX, (|))
+#define PMU_RESET_CAUSES \
+	COND_CODE_0(IS_EMPTY(PMU_RESET_CAUSES_), (PMU_RESET_CAUSES_), (0))
+#define WDT_RESET \
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(wwdt), (kPOWER_ResetSourceWdt), (0))
+#define RESET_CAUSES \
+	(PMU_RESET_CAUSES | WDT_RESET)
+
+	POWER_EnableResetSource(RESET_CAUSES);
+
 	/* Initialize clock */
 	clock_init();