drivers: uart_stm32: add DCache support in async DMA mode by using nocache memory regions #70503
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zephyrbot
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dcpleung,
Desvauxm-st,
gautierg-st and
GeorgeCGV
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| if DCACHE | ||
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| config DT_DEFINED_NOCACHE |
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Perhaps it's time to generalize the DT NOCACHE? Considering its usage here, in the SPI tests, and potentially by applications.
For example, by introducing related configs in
Line 385 in 414b3b7
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Yes, I already thought about it, it will simplify things. Thanks!
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Perhaps it's time to generalize the DT NOCACHE? Considering its usage here, in the SPI tests, and potentially by applications.
@GeorgeCGV Will do it in another PR for all drivers as soon as this one is merged.
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| #if defined(CONFIG_DCACHE) && defined(CONFIG_NOCACHE_MEMORY) | ||
| #define __NOCACHE __attribute__ ((__section__(".nocache"))) | ||
| #define NOCACHE_MEM 1 | ||
| #elif defined(CONFIG_DCACHE) && defined(CONFIG_DT_DEFINED_NOCACHE) | ||
| #define __NOCACHE __attribute__ ((__section__(CONFIG_DT_DEFINED_NOCACHE_NAME))) | ||
| #define NOCACHE_MEM 1 | ||
| #else | ||
| #define NOCACHE_MEM 0 | ||
| #endif /* CONFIG_NOCACHE_MEMORY */ |
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Open point, instead of modifiying the code, what about using the code relocation feature which will do the same operation behind the scene. For instance see: https://github.com/zephyrproject-rtos/zephyr/pull/65234/files.
Though, this solution doesn't seem to be compatible with use of ".nocache", so it could be a blocker
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interesting, will investigate.
| harness: ztest | ||
| harness_config: | ||
| fixture: gpio_loopback | ||
| depends_on: gpio |
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@dcpleung I'm surprise about this depends_on: gpio but I can see it all over this file. Is that expected ?
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Adapt the driver to verify if DMA buffers are located in noncacheable memory when DCache is activated, in order to avoid cache coherency issues. This is required until manual cache coherency management is implemented. Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add support for running tests with DCache enabled & put DMA buffers in a nocache memory region to avoid coherency issues. Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add test cases/configs for async DMA uart with DCache on STM32F7/H7 boards Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add the possibility to flash nucleo-f746zg board using west STM32CubeProgrammer runner. Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
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@dcpleung I'd like your opinion, specially on the test part, as this part is generic. |
Adapt the stm32 uart driver to verify if DMA buffers, used in async mode, are located in noncacheable memory when DCache is activated, in order to avoid cache coherency issues.
Modify
tests/drivers/uart_async_apitest to run with DCache enabled by putting DMA buffers in a nocache memory region.