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drivers: memc: add driver for is66wvq8m4 PSRAM #70620

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danieldegrasse
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Add driver for is66wvq8m4 PSRAM. This QSPI PSRAM is enabled on the RW612 BGA board, via the samples/drivers/memc sample.

Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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TYPO_SPELLING: 'SEPERATE' may be misspelled - perhaps 'SEPARATE'?
File:drivers/memc/memc_mcux_flexspi.c

The compliance failure here is expected- this macro definition is coming from the MCUX HAL, and it is misspelled there.

return ret;
}

buffer &= (~mask & 0xFFFF);
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Please consider GENMASK and FIELD_PREP().

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Switched to GENMASK, thanks for the suggestion. Not sure how I'd use FIELD_PREP here though? My understanding is that FIELD_PREP(0xEF,0x1F0) would expand to 0xF0, since the macro will shift and mask the field. In this function though, mask is the bitmask that should be cleared from the buffer, and set has already been shifted to the correct location (so FIELD_PREP(set, mask)) wouldn't make sense, right?

@@ -83,6 +83,7 @@ arduino_i2c: &flexcomm2 {
ahb-cacheable;
ahb-read-addr-opt;
rx-clock-source = <1>;
rx-clock-source-b = <3>;
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Is this change to the flexcomm node required?

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Yes- the IS66WVQ8M4 PSRAM uses a different clock source to send data (specifically the DQS pad of the flash chip). This is different from the mx25u51245g flash on port A, which uses a loopback clock from the DQS pad)

mmahadevan108
mmahadevan108 previously approved these changes Mar 22, 2024
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for IS66WVQ8M quadspi PSRAM on the RW612 BGA board, and
update board pin control to enable muxing PSRAM pins on the FlexSPI.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Since the RW612 BGA board's FlexSPI configuration prevents the board
from executing from flash while the PSRAM is configured (unless both are
configured by a bootloader prior to XIP), run the MEMC sample from
internal code SRAM, and write data to the external PSRAM block via the
FlexSPI.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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@dleach02 please take a look

@MaureenHelm MaureenHelm merged commit ce3c28b into zephyrproject-rtos:main May 7, 2024
21 of 22 checks passed
@danieldegrasse danieldegrasse deleted the feature/is66wv-psram branch May 7, 2024 20:07
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area: Devicetree Binding PR modifies or adds a Device Tree binding area: MEMC area: Samples Samples platform: NXP Drivers NXP Semiconductors, drivers platform: NXP NXP
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7 participants