Simd enablement #2945

shawnl · 2019-07-25T16:17:20Z

Not in scope:

new memory model for comptime
stack allocate vectors, so that addr-of vectors (&a[3]) can work, like they are supported in gcc-9

Some stuff is blocked on #447.

While this mostly follows #903, there are some decisions that had to be made, the biggest one is support both bit-wise and bool operations on bools, because a() and b() is differn't from a() & b(), as if a() returns true the first will not run b() and the second will. This is explained in the commit.

TODO

needs more tests of zero-length vectors
block exporting incompatible ABIs: 256-bit wide on pre-avx, and 512-bit wide on pre-avx512

shawnl · 2019-07-26T23:09:03Z

Some discussion on horizontal intrinsics in LLVM here #903 (comment) which effect #2698

std/math/fma.zig

data-man · 2019-07-28T11:23:35Z

var v: u32 = 5;
var x = @splat(4, v);

Can be changed to

var v: u32 = 5;
var x = @Vector(4, v);

?

doc/langref.html.in

src/all_types.hpp

src/codegen.cpp

daurnimator · 2019-07-28T11:32:08Z

src/ir.cpp

@@ -12734,6 +12925,30 @@ static IrInstruction *ir_analyze_cast(IrAnalyze *ira, IrInstruction *source_inst
        return ir_analyze_widen_or_shorten(ira, source_instr, value, wanted_type);
    }

+    // widening of vectors
+    // These are separate (while identical) as I am still not sure if this should not implicitely cast,
+    // but only explicitely cast. (i.e. with @cast, or @as, or @Vector(4, i32)(foo)),


Does this need deciding on before merge?

Also, typo: "explicitly"

src/ir_print.cpp

test/stage1/behavior/shuffle.zig

shawnl · 2019-07-28T12:26:03Z

@data-man I don't like that because the capital letter V means type.

doc/langref.html.in

andrewrk · 2019-11-02T06:45:43Z

The first item would be Array Accesses on Vectors. If you open a PR which only does this, I think we can get it merged swiftly. It seems everything else in this PR depends on that feature.

See #3575

This PR implements array access of vectors to mean element access, but it's planned for that to be how to dereference a vector of pointers.

I definitely am going to need this PR to be split into distinct smaller mergeable pieces.

shawnl · 2019-11-02T16:10:36Z

Yes I'm getting on it. However I disagree with this proposal. I don't see what is wrong with the way gcc-9 does it. I find your way confusing and unnecessarily different from use of arrays. As you discovered we can also make it work for odd-bit-widths if we change llvm's bit packing of vectors (when written out) to pad like arrays are (I don't really think this is a good idea however). El vie., 1 nov. 2019 23:45, Andrew Kelley <notifications@github.com> escribió:

…

The first item would be *Array Accesses on Vectors*. If you open a PR which only does this, I think we can get it merged swiftly. It seems everything else in this PR depends on that feature. See #3575 <#3575> This PR implements array access of vectors to mean element access, but it's planned for that to be how to dereference a vector of pointers. I definitely am going to need this PR to be split into distinct smaller mergeable pieces. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#2945?email_source=notifications&email_token=AAD4W4UMOSFGHZWQ4UUN6ATQRUO2BA5CNFSM4IG4JEO2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEC4VHZA#issuecomment-549016548>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAD4W4TNSIZYLIDK6UDWQP3QRUO2BANCNFSM4IG4JEOQ> .

shawnl · 2019-11-05T21:11:50Z

The lowering to @shuffle, @gather, and @scatter of loads and stores got dropped while re-basing this.

If the integer fits in the significand (including the signed bit because of a edge case resulting from the difference between twos-complement and ones-complement), then cast to float is lossless.

This will allow alot more integer code to just magically work with vectors of integers, et cetera.

https://llvm.org/docs/LangRef.html#zext-to-instruction The ‘zext’ instruction takes a value to cast, and a type to cast it to. Both types must be of integer types, or vectors of the same number of integers. **The bit size of the value must be smaller than the bit size of the destination type, ty2.** The codegen was invalid.

v2: fixup dest_type when value is nullptr

No comptime support yet, that will enough work that it needs to be its own patch series. v2: ir_analyze_masked_vector for use by vector indexing

Why ^, &, |, and ~ instead of !=, and, or, !? Consider: a() and b() If a() returns @vector(2, bool)([_]bool{false, false}), is b() run? How about if a() returns @vector(2, bool)([_]bool{false, true})? Making this defined would be slow, confusing, involve hidden control flow, and require putting the any() all() none() branching into the language. Even if a() and b() return "bool" these are different: a() and b() a() & b() ----- I would like to throw a good error when a vector of bools is passed, but the current architecture prevents that.

@truncate

…unc), with safety checks. Finishing this depends on ziglang#1757. I'd rather not re-work ir_gen_node_raw for explicit casts (signed to unsigned, and safe narrowing casts) when that is upcoming. v2: @truncate can now take a scalar type

@sin

@sin @cos @exp @exp2 @ln @log2 @log10 @Fabs @floor @ceil @trunc @round @sqrt

v2: do not emit libmvec when it does exist on the platform v3: do what is written above

Can't test for larger vectors (256-bit and 512-bit because of confusion with passing on stack and passing in registers (that don'y always exist). See ziglang#1481 (comment) ARM uses sret for vector arguments, and those are runtime. I don't understand what that assert was for.

andrewrk · 2019-11-27T21:36:47Z

This PR won't be merged, but I'm definitely interested in the smaller PRs that bring these commits in 1 at a time. I'll leave it up to @shawnl (or anyone else!) to track this fork and do the work of slowly upstreaming it.

shawnl force-pushed the simd5 branch 3 times, most recently from c32bb99 to 4db2a1c Compare July 26, 2019 03:30

data-man reviewed Jul 28, 2019

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shawnl force-pushed the simd5 branch 4 times, most recently from 7b458ce to 520d2a3 Compare August 2, 2019 18:06

shawnl force-pushed the simd5 branch 7 times, most recently from 5283ce3 to e5292c0 Compare August 6, 2019 18:50

shawnl marked this pull request as ready for review August 6, 2019 22:00

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shawnl force-pushed the simd5 branch 3 times, most recently from ccad74f to 8a76f14 Compare August 16, 2019 02:06

andrewrk added this to the 0.5.0 milestone Aug 19, 2019

shawnl force-pushed the simd5 branch from 8a76f14 to d872d9c Compare August 23, 2019 13:33

shawnl force-pushed the simd5 branch 4 times, most recently from ec301d1 to 44c9b47 Compare September 9, 2019 22:25

andrewrk mentioned this pull request Nov 2, 2019

Vector element access #3575

Closed

shawnl force-pushed the simd5 branch from 10ea3ed to 16fd3ae Compare November 3, 2019 03:07

shawnl mentioned this pull request Nov 3, 2019

Simd array #3580

Closed

shawnl force-pushed the simd5 branch from 16fd3ae to c924149 Compare November 5, 2019 21:10

shawnl added 18 commits November 21, 2019 05:23

@floatCast for vectors, and allow safe casts from non-comptime integers.

6f80beb

If the integer fits in the significand (including the signed bit because of a edge case resulting from the difference between twos-complement and ones-complement), then cast to float is lossless.

Vector type field access (len, and all those of the child element)

f005607

This will allow alot more integer code to just magically work with vectors of integers, et cetera.

std: branching on vectors, all(), any(), and none(), and select()

44b140f

@bitcast

203408d

v2: fixup dest_type when value is nullptr

fixup comptime @byteswap to have the types

79e306d

@gather and @scatter

46d10d3

No comptime support yet, that will enough work that it needs to be its own patch series. v2: ir_analyze_masked_vector for use by vector indexing

stage1/codegen: vector_all and vector_any helpers

be5a24e

get_c_type for vectors

174a6d4

docs: @inttofloat @floatCast

25c5ad1

emit error for reachable compile error (vector length mix-match)

df35065

work around bizarre bug (attempt 6)

f1360b3

stage1: accept vectors for all the float operations we have

727c420

@sin @cos @exp @exp2 @ln @log2 @log10 @Fabs @floor @ceil @trunc @round @sqrt

rem_zero fixup

60ae741

update glibc to include libmvec

bf57996

v2: do not emit libmvec when it does exist on the platform v3: do what is written above

shawnl force-pushed the simd5 branch from c924149 to 10c4c4a Compare November 21, 2019 01:29

andrewrk closed this Nov 27, 2019

data-man mentioned this pull request Dec 19, 2019

Add len field to vectors #3941

Closed

daurnimator added the stage1 The process of building from source via WebAssembly and the C backend. label Dec 19, 2019

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Simd enablement #2945

Simd enablement #2945

shawnl commented Jul 25, 2019 •

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Simd enablement #2945

Simd enablement #2945

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