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A basic introduction of Verilog/VHDL design using Myhdl based on Python.

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README.md

README.md

 
 

adder_python.py

adder_python.py

 
 

adder_wave(adder.vcd).png

adder_wave(adder.vcd).png

 
 

dff_python.py

dff_python.py

 
 

dff_verilog.v

dff_verilog.v

 
 

dff_vhdl.vhd

dff_vhdl.vhd

 
 

dff_wave(test_dff.vcd).png

dff_wave(test_dff.vcd).png

 
 

pck_myhdl_090.vhd

pck_myhdl_090.vhd

 
 

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A-Verilog-VHDL-design-using-python

MyHDL transforms Python to hardware description languages, Verilog or VHDL, while providing convinient platform to test the design functions. This repository takes a design including two examples, a delay flip-flop (DFF) as a sequential logic circuit, and an adder as a combinational logic circuit.

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A basic introduction of Verilog/VHDL design using Myhdl based on Python.

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