Skip to content
View zslwyuan's full-sized avatar
🎯
Focusing
🎯
Focusing
  • HKUST
  • Hong Kong

Highlights

  • Pro
Block or Report

Block or report zslwyuan

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. AMF-Placer AMF-Placer Public

    AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

    C++ 87 18

  2. Light-HLS Light-HLS Public

    Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

    C++ 52 21

  3. PAAS_V1.0 PAAS_V1.0 Public

    PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

    Ada 41 16

  4. Hi-DMM Hi-DMM Public

    Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

    VHDL 25 9

  5. LLVM-9.0-Learner-Tutorial LLVM-9.0-Learner-Tutorial Public

    A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

    C++ 98 23

  6. Basic-SIMD-Processor-Verilog-Tutorial Basic-SIMD-Processor-Verilog-Tutorial Public

    Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

    Verilog 102 31