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OpenCL_implementation
config_controller
driver-scheduler
static_prebuilt
COPYING
README.md

README.md

zucl_fsp2018

  • Available resources for 1 PR slot:

Available
CLB LUTs 32640
LUT as Logic 32640
LUT as Memory 17280
CLB Registers 65280
Register as Flip Flop 65280
Register as Latch 65280
CARRY8 4080
F7 Muxes 16320
F8 Muxes 8160
F9 Muxes 4080
Block RAM Tile 108
RAMB36/FIFO 108
RAMB18 216
DSPs 336

Contact: if you have any concern, please write to me at khoa.pham@manchester.ac.uk!