Update SystemVerilog API list to 2017, issue #474.

readme.md

@@ -132,7 +132,7 @@ Latest development builds (artifacts in Release configuration for each compiler
 	* Visual Basic, VB6, VB.NET
 	* VBScript
 	* VHDL
-	* Verilog HDL, up to [Verilog](tools/lang/Verilog.v) 2005 and [SystemVerilog](tools/lang/SystemVerilog.sv) 2012.
+	* Verilog HDL, up to [Verilog](tools/lang/Verilog.v) 2005 and [SystemVerilog](tools/lang/SystemVerilog.sv) 2017.
 	* [Vim Script](tools/lang/Vim.vim)
 	* [WebAssembly](https://github.com/WebAssembly/wabt/blob/main/src/lexer-keywords.txt), up to wabt 1.0.
 	* XML Document, [Screenshots](https://github.com/zufuliu/notepad2/wiki/Screenshots#xml)

scintilla/lexers/LexVerilog.cxx

@@ -47,11 +47,12 @@ struct EscapeSequence {
 
 enum {
 	VerilogLineStateMaskLineComment = 1,
-	VerilogLineStateMaskDirective = 2,
+	VerilogLineStateMaskDirective = 1 << 1,
 	// extern, typedef, import, export, pure, bind
-	VerilogLineStateMaskDeclaration = 4,
+	VerilogLineStateMaskDeclaration = 1 << 2,
 	// (* attribute *)
-	VerilogLineStateMaskAttribute = 8,
+	VerilogLineStateMaskAttribute = 1 << 3,
+	VerilogLineStateLineContinuation = 1 << 4,
 };
 
 //KeywordIndex++Autogenerated -- start of section automatically generated
@@ -182,6 +183,7 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 
 	bool insideUrl = false;
 	bool angleQuote = false; // `include <path>
+	bool backtickQuote = false; // `" `"
 	int visibleChars = 0;
 	KeywordType kwType = KeywordType::None;
 	int chBeforeIdentifier = 0;
@@ -192,17 +194,22 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 	StyleContext sc(startPos, lengthDoc, initStyle, styler);
 	if (sc.currentLine > 0) {
 		lineState = styler.GetLineState(sc.currentLine - 1);
-		parentCount = lineState >> 8;
-		kwType = static_cast<KeywordType>((lineState >> 4) & 15);
-		lineState &= VerilogLineStateMaskDeclaration | VerilogLineStateMaskAttribute;
+		/*
+		8: lineState
+		4: kwType
+		20: parentCount
+		*/
+		parentCount = lineState >> 12;
+		kwType = static_cast<KeywordType>((lineState >> 8) & 15);
+		lineState &= VerilogLineStateMaskDeclaration | VerilogLineStateMaskAttribute | VerilogLineStateLineContinuation;
 	}
 	if (startPos != 0 && IsSpaceEquiv(initStyle)) {
 		LookbackNonWhite(styler, startPos, SCE_V_TASKMARKER, chPrevNonWhite, stylePrevNonWhite);
 	}
 
 	while (sc.More()) {
 		if (sc.atLineStart) {
-			lineState &= VerilogLineStateMaskDeclaration | VerilogLineStateMaskAttribute;
+			lineState &= VerilogLineStateMaskDeclaration | VerilogLineStateMaskAttribute | VerilogLineStateLineContinuation;
 			visibleChars = 0;
 			angleQuote = false;
 			if (kwType == KeywordType::Macro) {
@@ -223,15 +230,25 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 
 		case SCE_V_STRING:
 			if (sc.atLineStart) {
-				sc.SetState(SCE_V_DEFAULT);
-			} else if (sc.ch == (angleQuote ? '>' : '\"')) {
+				if (lineState & VerilogLineStateLineContinuation) {
+					lineState &= ~VerilogLineStateLineContinuation;
+				} else {
+					sc.SetState(SCE_V_DEFAULT);
+					break;
+				}
+			}
+			if (sc.ch == (angleQuote ? '>' : '\"')) {
 				angleQuote = false;
 				sc.ForwardSetState(SCE_V_DEFAULT);
 			} else if (!angleQuote) {
 				if (sc.ch == '\\') {
-					escSeq.resetEscapeState(sc.chNext);
-					sc.SetState(SCE_V_ESCAPECHAR);
-					sc.Forward();
+					if (IsEOLChar(sc.chNext)) {
+						lineState |= VerilogLineStateLineContinuation;
+					} else {
+						escSeq.resetEscapeState(sc.chNext);
+						sc.SetState(SCE_V_ESCAPECHAR);
+						sc.Forward();
+					}
 				} else if (sc.ch == '%') {
 					const Sci_Position length = CheckFormatSpecifier(sc, styler, insideUrl);
 					if (length != 0) {
@@ -244,6 +261,10 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 					insideUrl = true;
 				} else if (insideUrl && IsInvalidUrlChar(sc.ch)) {
 					insideUrl = false;
+				} else if (backtickQuote && sc.Match('`', '\\', '`', '\"')) {
+					escSeq.digitsLeft = 1;
+					sc.SetState(SCE_V_ESCAPECHAR);
+					sc.Advance(3);
 				}
 			}
 			break;
@@ -298,7 +319,7 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 					} else if (prevWord == KeywordType::Macro) {
 						sc.ChangeState(SCE_V_MACRO);
 					} else if (sc.state == SCE_V_IDENTIFIER && chBeforeIdentifier != '#') {
-						// # delay
+						// # delay, ## delay
 						if (keywordLists[KeywordIndex_DataType]->InList(s)) {
 							sc.ChangeState(SCE_V_DATATYPE);
 						} else if (keywordLists[KeywordIndex_CodeFolding]->InList(s)) {
@@ -337,7 +358,7 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 						}
 					}
 					if (sc.state == SCE_V_IDENTIFIER || sc.state == SCE_V_ESCAPE_IDENTIFIER) {
-						if (sc.ch == ':' && sc.chNext != ':' && visibleChars == sc.LengthCurrent()) {
+						if (parentCount == 0 && sc.ch == ':' && sc.chNext != ':' && visibleChars == sc.LengthCurrent()) {
 							sc.ChangeState(SCE_V_LABEL);
 						} else if (lineState & VerilogLineStateMaskAttribute) {
 							if (chBeforeIdentifier != '=') {
@@ -401,6 +422,7 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 			} else if (sc.ch == '\"') {
 				insideUrl = false;
 				angleQuote = false;
+				backtickQuote = sc.chPrev == '`' && (lineState & VerilogLineStateMaskDirective);
 				sc.SetState(SCE_V_STRING);
 			} else if (sc.ch == '<') {
 				sc.SetState(angleQuote ? SCE_V_STRING : SCE_V_OPERATOR);
@@ -446,7 +468,7 @@ void ColouriseVerilogDoc(Sci_PositionU startPos, Sci_Position lengthDoc, int ini
 			}
 		}
 		if (sc.atLineEnd) {
-			styler.SetLineState(sc.currentLine, lineState | (static_cast<int>(kwType) << 4) | (parentCount << 8));
+			styler.SetLineState(sc.currentLine, lineState | (static_cast<int>(kwType) << 8) | (parentCount << 12));
 		}
 		sc.Forward();
 	}

src/EditLexers/stlVerilog.c

@@ -70,13 +70,17 @@ static KEYWORDLIST Keywords_Verilog = {{
 "warning( width( write( writeb( writeh( writememb( writememh( writeo( "
 
 , // 5 misc
-"PATHPULSE$ STDERR STDIN STDOUT accept_on( and( atobin( atohex( atoi( atooct( atoreal( bintoa( compare( constraint_mode( "
-"delete( exists( find( find_first( find_first_index( find_index( find_last( find_last_index( first( first_match( "
-"get( get_randstate( getc( hextoa( icompare( index( insert( itoa( last( len( mailbox max( min( name( new( next( num( "
-"octtoa( or( peek( pop_back( pop_front( post_randomize( pre_randomize( prev( product( push_back( push_front( put( putc( "
-"randomize( realtoa( reject_on( reverse( rsort( "
-"semaphore set_randstate( shuffle( size( sort( srandom( std substr( sum( sync_accept_on( sync_reject_on( "
-"tolower( toupper( try_get( try_peek( try_put( unique( unique_index( xor( "
+"PATHPULSE$ STDERR STDIN STDOUT accept_on( and( assert( assume( atobin( atohex( atoi( atooct( atoreal( await( bintoa( "
+"compare( constraint_mode( cover( delete( exists( expect( "
+"find( find_first( find_first_index( find_index( find_last( find_last_index( first( first_match( "
+"get( get_coverage( get_inst_coverage( get_randstate( getc( hextoa( icompare( index( insert( itoa( kill( last( len( "
+"mailbox max( min( name( new( next( num( octtoa( or( "
+"peek( pop_back( pop_front( post_randomize( pre_randomize( prev( process product( property( "
+"push_back( push_front( put( putc( "
+"rand_mode( randomize( realtoa( reject_on( resume( reverse( rsort( "
+"sample( self( semaphore sequence( set_inst_name( set_randstate( shuffle( size( sort( srandom( start( status( std stop( "
+"substr( sum( suspend( sync_accept_on( sync_reject_on( "
+"tolower( toupper( try_get( try_peek( try_put( unique( unique_index( wait_order( xor( "
 
 , NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
 //--Autogenerated -- end of section automatically generated

tools/lang/SystemVerilog.sv

@@ -1,4 +1,4 @@
-// SystemVerilog 2012
+// SystemVerilog 2017
 
 //! keywords			=======================================================
 accept_on alias always always_comb always_ff always_latch assert assign assume automatic
@@ -50,8 +50,6 @@ endclass
 disable fork;
 wait fork;
 bind + function float faddif(int, float); // Operator overloading
-assert property(property_spec);
-cover sequence(sequence_expr)
 default clocking clocking_identifier;
 rand join // Random sequence generation
 export "DPI-C" function f;
@@ -190,6 +188,18 @@ or()
 xor()
 int_or_index_type index(int dimension = 1);
 
+class process;
+	static process self();
+	state status();
+	void kill();
+	/*task*/ await();
+	void suspend();
+	void resume();
+	void srandom(int seed);
+	string get_randstate();
+	void set_randstate(string state);
+endclass
+
 class semaphore
 	new(int keyCount = 0);
 	void put(int keyCount = 1);
@@ -208,16 +218,25 @@ class mailbox
 	int try_peek(ref singular message);
 endclass
 
+wait_order(hierarchical_identifier {, hierarchical_identifier}) action_block
+assert(expression) action_block
+assume(expression) action_block
+cover(expression) statement_or_null
+assert property(property_spec);
+cover sequence(sequence_expr) statement_or_null
+
 first_match(sequence_expr {, sequence_match_item})
 accept_on(expression_or_dist) property_expr
 reject_on(expression_or_dist) property_expr
 sync_accept_on(expression_or_dist) property_expr
 sync_reject_on(expression_or_dist) property_expr
+expect(property_spec) action_block
 
 // Randomization methods
 int randomize();
 void pre_randomize();
 void post_randomize();
+rand_mode(bit on_off);
 constraint_mode(bit on_off);
 $urandom
 $urandom(int seed)
@@ -226,6 +245,16 @@ void srandom(int seed);
 string get_randstate();
 void set_randstate(string state);
 
+// Predefined coverage methods
+void sample()
+real get_coverage()
+real get_coverage(ref int, ref int)
+real get_inst_coverage()
+real get_inst_coverage(ref int, ref int)
+void set_inst_name(string)
+void start()
+void stop()
+
 //! System task and function		===========================================
 // Simulation control tasks
 $exit