Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
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Updated
Jun 1, 2024 - Bluespec
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
Verilator open-source SystemVerilog simulator and lint system
Veryl: A Modern Hardware Description Language
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
The home of PHPFlasher, a PHP library for easy, customizable notification messages in web development projects. With implementations for Laravel, Symfony, and standalone use, PHPFlasher simplifies the process of adding notifications to web applications. The mono repository enables efficient collaboration and version control among developers.
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A flexible and scalable development platform for modern FPGA projects.
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
VeeR EL2 Core
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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