🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Updated
May 31, 2024 - C
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform
System on Chip toolkit for Amaranth HDL
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
🌌 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Embedded Systems Geeks Guadalajara - Collaboration Space
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Hardware Abstraction Layer for Atmosic SoCs in the Zephyr Environment
Chisel implementation of Neural Processing Unit for System on the Chip
Examples of using Litex on an Alchitry Cu board
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
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