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L1T multiboard uGT part1 (80x) #15201

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merged 2 commits into from Jul 22, 2016
Merged

L1T multiboard uGT part1 (80x) #15201

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2d8bdf6
First changes for multiboard uGT operation
blwiner May 24, 2016
3601fd6
Go back to not packing ExtBlk when packing uGT payloads
rekovic Jun 1, 2016
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41 changes: 22 additions & 19 deletions EventFilter/L1TRawToDigi/src/implementations_stage2/GTSetup.cc
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Expand Up @@ -41,6 +41,7 @@ namespace l1t {
PackerFactory::get()->make("stage2::GlobalAlgBlkPacker"),
//PackerFactory::get()->make("stage2::GlobalExtBlkPacker")
};

}

return res;
Expand Down Expand Up @@ -76,25 +77,27 @@ namespace l1t {
UnpackerMap res;

if (fed == 1404) {

// From the rx buffers
res[0] = muon_unp;
res[2] = muon_unp;
res[4] = muon_unp;
res[6] = muon_unp;
res[8] = egamma_unp;
res[10] = egamma_unp;
res[12] = jet_unp;
res[14] = jet_unp;
res[16] = tau_unp;
res[18] = tau_unp;
res[20] = etsum_unp;
res[24] = ext_unp;
//res[22] = empty link no data
res[26] = ext_unp;
res[28] = ext_unp;
res[30] = ext_unp;


//only unpack first uGT board for the inputs (single copy)
if(amc == 1) {
// From the rx buffers
res[0] = muon_unp;
res[2] = muon_unp;
res[4] = muon_unp;
res[6] = muon_unp;
res[8] = egamma_unp;
res[10] = egamma_unp;
res[12] = jet_unp;
res[14] = jet_unp;
res[16] = tau_unp;
res[18] = tau_unp;
res[20] = etsum_unp;
res[24] = ext_unp;
//res[22] = empty link no data
res[26] = ext_unp;
res[28] = ext_unp;
res[30] = ext_unp;
}

//From tx buffers
res[33] = alg_unp;
Expand Down
37 changes: 25 additions & 12 deletions EventFilter/L1TRawToDigi/src/implementations_stage2/GlobalAlgBlkUnpacker.cc
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Expand Up @@ -21,13 +21,19 @@ namespace stage2 {
GlobalAlgBlkUnpacker::unpack(const Block& block, UnpackerCollections *coll)
{

LogDebug("L1T") << "Block ID = " << block.header().getID() << " size = " << block.header().getSize();
LogDebug("L1T") << "AMCNo " << block.amc().getAMCNumber() << " Block ID = " << block.header().getID() << " size = " << block.header().getSize();

// ================================================================================
//Should this be configured someplace?
unsigned int wdPerBX = 6;
unsigned int wdPerBX = 6;
unsigned int initialBlkID = 33; //first block of inital alg bits
unsigned int intermBlkID = 39; //first block of alg bits after intermediate step
unsigned int finalBlkID = 45; //first block of final alg bits
unsigned int intermBlkID = 39; //first block of alg bits after intermediate step
unsigned int finalBlkID = 45; //first block of final alg bits
// ================================================================================


unsigned int uGTBoard = block.amc().getAMCNumber() - 1;


int nBX = int(ceil(block.header().getSize() / 6.)); // FOR GT Not sure what we have here...put at 6 because of 6 frames

Expand All @@ -50,10 +56,10 @@ namespace stage2 {
for (int bx=firstBX; bx<=lastBX; bx++){


// If this is the first block, instantiate GlobalAlg so it is there to fill from mult. blocks
if(block.header().getID()==initialBlkID) {
// If this is the first block on first board, instantiate GlobalAlg so it is there to fill from mult. blocks
if(block.header().getID()==initialBlkID && uGTBoard == 0 ) {

LogDebug("L1T") << "Creating GT Algorithm Block for BX =" << bx;
LogDebug("L1T") << "Creating GT Algorithm Block for BX =" << bx << std::endl;
GlobalAlgBlk talg = GlobalAlgBlk();
res_->push_back(bx,talg);

Expand All @@ -78,8 +84,9 @@ namespace stage2 {
for(unsigned int bt=0; bt<32; bt++) {
int val = ((raw_data >> bt) & 0x1);
unsigned int algBit = bt+wd*32+algOffset;
if(val==1 && algBit < alg.maxPhysicsTriggers) { //FIX ME...get dimension from object
LogDebug("L1T") << "Found valid alg bit ("<< algBit <<") on bit ("<<bt<<") word ("<<wd<<") algOffset ("<<algOffset<<") block ID ("<< block.header().getID() <<")" <<std::endl;

if(val==1 && algBit < alg.maxPhysicsTriggers) {
LogDebug("L1T") << "Found valid alg bit ("<< algBit <<") on bit ("<<bt<<") word ("<<wd<<") algOffset ("<<algOffset<<") block ID ("<< block.header().getID() <<")" << " Board# " << uGTBoard <<std::endl;
if(block.header().getID()<initialBlkID+5) {
alg.setAlgoDecisionInitial(algBit,true);
} else if(block.header().getID()<intermBlkID+5) {
Expand All @@ -88,7 +95,7 @@ namespace stage2 {
alg.setAlgoDecisionFinal(algBit,true);
}
} else if(val==1) {
LogDebug("L1T") << "Found invalid alg bit ("<< algBit <<") out of range (128) on bit ("<<bt<<") word ("<<wd<<") algOffset ("<<algOffset<<") block ID ("<< block.header().getID() <<")" <<std::endl;
LogDebug("L1T") << "Found invalid alg bit ("<< algBit <<") out of range on bit ("<<bt<<") word ("<<wd<<") algOffset ("<<algOffset<<") block ID ("<< block.header().getID() <<")" <<std::endl;
}
}

Expand All @@ -99,8 +106,7 @@ namespace stage2 {
if(wd==5) alg.setL1FirmwareUUID(raw_data);

} else if(block.header().getID()==finalBlkID+4 && wd==4) {
//This is the FINOR
if ( (raw_data & 0x10000)>>16 ) alg.setFinalOR(true);
//Get the local FINORs and Veto...Global FINOR calculated below
if ( (raw_data & 0x100)>> 8 ) alg.setFinalORVeto(true);
if ( (raw_data & 0x1)>> 0 ) alg.setFinalORPreVeto(true);
LogDebug("L1T") << " Packing the FinalOR " << wd << " 0x" << hex << raw_data << endl;
Expand All @@ -111,6 +117,13 @@ namespace stage2 {
}
}

//Redetermine Final (multiboard) FINOR
if(alg.getFinalORPreVeto() & !alg.getFinalORVeto()) {
alg.setFinalOR(true);
} else {
alg.setFinalOR(false); //be explicit and must set to false if we find a board with veto set.
}

// Put the object back into place (Must be better way)
res_->set(bx,0,alg);

Expand Down