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Put LCT related enums in CSCConstants #21650

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merged 7 commits into from Dec 19, 2017
Merged

Put LCT related enums in CSCConstants #21650

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68364cf
put readout windows in CSCConstants
Dec 5, 2017
7243ce5
put enums in CSCConstants
Dec 6, 2017
5f083f1
put enums in CSCConstants
Dec 6, 2017
844dcf9
max ME11 halfstrip enum
Dec 6, 2017
9a094a6
extra lct enums
Dec 6, 2017
78b279b
bugfix
Dec 6, 2017
c13926b
suggestions by UCLA
Dec 11, 2017
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72 changes: 62 additions & 10 deletions L1Trigger/CSCCommonTrigger/interface/CSCConstants.h
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Expand Up @@ -11,22 +11,74 @@
class CSCConstants
{
public:
enum WG_and_Strip { MAX_NUM_WIRES = 119, MAX_NUM_STRIPS = 80, MAX_NUM_STRIPS_7CFEBS = 112,
NUM_DI_STRIPS = 40+1, // Add 1 to allow for staggering of strips
NUM_HALF_STRIPS = 160+1, NUM_HALF_STRIPS_7CFEBS = 224+1};
enum CFEB_Info {
//Maximum number of cathode front-end boards
MAX_CFEBS = 5,
};

enum FPGA_Latency{
CLCT_EMUL_TIME_OFFSET = 3,
ALCT_EMUL_TIME_OFFSET = 6
};

// Note: WIRE means actually "wiregroup" here
enum WG_and_Strip {
MAX_NUM_WIRES = 119,
MAX_WIRES_ME11 = 48,
MAX_NUM_STRIPS = 80,
MAX_NUM_STRIPS_7CFEBS = 112,
NUM_DI_STRIPS = 40+1, // Add 1 to allow for staggering of strips
NUM_HALF_STRIPS = 160+1,
NUM_HALF_STRIPS_7CFEBS = 224+1,
// each CFEB reads out 8 distrips, 16 strips or 32 halfstrips
NUM_DISTRIPS_PER_CFEB = 8,
NUM_STRIPS_PER_CFEB = 16,
NUM_HALF_STRIPS_PER_CFEB = 32,
// max halfstrip number in ME1/1 chambers
// All ME1A readout by 1 CFEB -> 32 -1
MAX_HALF_STRIP_ME1A_GANGED = 31,
// All ME1A readout by 3 CFEBs -> 3*32 -1
MAX_HALF_STRIP_ME1A_UNGANGED = 95,
// All ME1B readout by 4 CFEBs -> 4*32 -1
MAX_HALF_STRIP_ME1B = 127
};

// CSCs have 6 layers. The key (refernce) layer is the third layer
enum Layer_Info { NUM_LAYERS = 6, KEY_CLCT_LAYER = 3, KEY_CLCT_LAYER_PRE_TMB07 = 4, KEY_ALCT_LAYER = 3 };
enum Layer_Info {
NUM_LAYERS = 6,
KEY_CLCT_LAYER = 3,
KEY_CLCT_LAYER_PRE_TMB07 = 4,
KEY_ALCT_LAYER = 3 };

// Both ALCT and CLCTs have patterns. CLCTs have a better granularity than ALCTs, thus more patterns
enum Pattern_Info { NUM_ALCT_PATTERNS = 3, NUM_CLCT_PATTERNS = 11, NUM_CLCT_PATTERNS_PRE_TMB07 = 8 };

enum Digis_Info { MAX_DIGIS_PER_ALCT = 10, MAX_DIGIS_PER_CLCT = 8 };
enum Pattern_Info {
NUM_ALCT_PATTERNS = 3,
NUM_CLCT_PATTERNS = 11,
NUM_CLCT_PATTERNS_PRE_TMB07 = 8,
// Max number of wires participating in a pattern
MAX_WIRES_IN_PATTERN = 14,
// Max number of strips participating in a pattern
MAX_STRIPS_IN_PATTERN = 26,
// Max number of halfstrips participating in a pattern
MAX_HALFSTRIPS_IN_PATTERN = 42};

// Each CSC can send up to 2 LCTs to the MPC.
// An MPC receives up to 18 LCTs from 9 CSCs in the trigger sector
enum LCT_stubs{ MAX_LCTS_PER_CSC = 2, MAX_LCTS_PER_MPC = 18 };
enum Digis_Info {
MAX_DIGIS_PER_ALCT = 10,
MAX_DIGIS_PER_CLCT = 8 };

enum LCT_stubs{
// CSC local trigger considers 4-bit BX window (16 numbers) in the readout
MAX_CLCT_TBINS = 16,
MAX_ALCT_TBINS = 16,
MAX_LCT_TBINS = 16,
// Each CLCT processor can snd up to 2 CLCTs to TMB
MAX_CLCTS_PER_PROCESSOR = 2,
// Each ALCT processor can snd up to 2 ALCTs to TMB
MAX_ALCTS_PER_PROCESSOR = 2,
// Each CSC can send up to 2 LCTs to the MPC.
MAX_LCTS_PER_CSC = 2,
// An MPC receives up to 18 LCTs from 9 CSCs in the trigger sector
MAX_LCTS_PER_MPC = 18 };
};

#endif
57 changes: 27 additions & 30 deletions L1Trigger/CSCTriggerPrimitives/src/CSCAnodeLCTProcessor.cc
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Expand Up @@ -40,7 +40,7 @@
patterns A and B.
pattern_envelope[0][i]=layer;
pattern_envelope[1+MEposition][i]=key_wire offset. */
const int CSCAnodeLCTProcessor::pattern_envelope[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES] = {
const int CSCAnodeLCTProcessor::pattern_envelope[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN] = {
//Layer
{ 0, 0, 0,
1, 1,
Expand All @@ -67,7 +67,7 @@ const int CSCAnodeLCTProcessor::pattern_envelope[CSCConstants::NUM_ALCT_PATTERNS
};

// time averaging weights for pattern (used for SLHC version)
const int CSCAnodeLCTProcessor::time_weights[NUM_PATTERN_WIRES] =
const int CSCAnodeLCTProcessor::time_weights[CSCConstants::MAX_WIRES_IN_PATTERN] =
//Layer
{ 0, 1, 1,
1, 2,
Expand All @@ -81,7 +81,7 @@ const int CSCAnodeLCTProcessor::time_weights[NUM_PATTERN_WIRES] =
// and collision patterns A and B. These masks were meant to be the default
// ones in early 200X, but were never implemented because of limited FPGA
// resources.
const int CSCAnodeLCTProcessor::pattern_mask_slim[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES] = {
const int CSCAnodeLCTProcessor::pattern_mask_slim[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN] = {
// Accelerator pattern
{0, 0, 1,
0, 1,
Expand Down Expand Up @@ -109,7 +109,7 @@ const int CSCAnodeLCTProcessor::pattern_mask_slim[CSCConstants::NUM_ALCT_PATTERN

// Since the test beams in 2003, both collision patterns are "completely
// open". This is our current default.
const int CSCAnodeLCTProcessor::pattern_mask_open[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES] = {
const int CSCAnodeLCTProcessor::pattern_mask_open[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN] = {
// Accelerator pattern
{0, 0, 1,
0, 1,
Expand All @@ -136,7 +136,7 @@ const int CSCAnodeLCTProcessor::pattern_mask_open[CSCConstants::NUM_ALCT_PATTERN
};

// Special option for narrow pattern for ring 1 stations
const int CSCAnodeLCTProcessor::pattern_mask_r1[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES] = {
const int CSCAnodeLCTProcessor::pattern_mask_r1[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN] = {
// Accelerator pattern
{0, 0, 1,
0, 1,
Expand Down Expand Up @@ -224,8 +224,7 @@ CSCAnodeLCTProcessor::CSCAnodeLCTProcessor(unsigned endcap, unsigned station,

// separate handle for early time bins
early_tbins = conf.getParameter<int>("alctEarlyTbins");
int fpga_latency = 6;
if (early_tbins<0) early_tbins = fifo_pretrig - fpga_latency;
if (early_tbins<0) early_tbins = fifo_pretrig - CSCConstants::ALCT_EMUL_TIME_OFFSET;

// delta BX time depth for ghostCancellationLogic
ghost_cancellation_bx_depth = conf.getParameter<int>("alctGhostCancellationBxDepth");
Expand Down Expand Up @@ -319,7 +318,7 @@ CSCAnodeLCTProcessor::CSCAnodeLCTProcessor() :
void CSCAnodeLCTProcessor::loadPatternMask() {
// Load appropriate pattern mask.
for (int i_patt = 0; i_patt < CSCConstants::NUM_ALCT_PATTERNS; i_patt++) {
for (int i_wire = 0; i_wire < NUM_PATTERN_WIRES; i_wire++) {
for (int i_wire = 0; i_wire < CSCConstants::MAX_WIRES_IN_PATTERN; i_wire++) {
if (isMTCC || isTMB07) {
pattern_mask[i_patt][i_wire] = pattern_mask_open[i_patt][i_wire];
if (narrow_mask_r1 && (theRing == 1 || theRing == 4))
Expand Down Expand Up @@ -384,7 +383,7 @@ void CSCAnodeLCTProcessor::checkConfigParameters() {
static const unsigned int max_nplanes_hit_accel_pattern = 1 << 3;
static const unsigned int max_trig_mode = 1 << 2;
static const unsigned int max_accel_mode = 1 << 2;
static const unsigned int max_l1a_window_width = MAX_ALCT_BINS; // 4 bits
static const unsigned int max_l1a_window_width = CSCConstants::MAX_ALCT_TBINS; // 4 bits

// Checks.
if (fifo_tbins >= max_fifo_tbins) {
Expand Down Expand Up @@ -472,7 +471,7 @@ void CSCAnodeLCTProcessor::checkConfigParameters() {
}

void CSCAnodeLCTProcessor::clear() {
for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
bestALCT[bx].clear();
secondALCT[bx].clear();
}
Expand All @@ -492,8 +491,6 @@ CSCAnodeLCTProcessor::run(const CSCWireDigiCollection* wiredc) {
// This is the main routine for normal running. It gets wire times
// from the wire digis and then passes them on to another run() function.

// clear(); // redundant; called by L1MuCSCMotherboard.

static std::atomic<bool> config_dumped{false};
if ((infoV > 0 || isSLHC) && !config_dumped) {
//std::cout<<"**** ALCT run parameters dump ****"<<std::endl;
Expand Down Expand Up @@ -833,7 +830,7 @@ bool CSCAnodeLCTProcessor::preTrigger(const int key_wire, const int start_bx) {
hit_layer[i_layer] = false;
layers_hit = 0;

for (int i_wire = 0; i_wire < NUM_PATTERN_WIRES; i_wire++){
for (int i_wire = 0; i_wire < CSCConstants::MAX_WIRES_IN_PATTERN; i_wire++){
if (pattern_mask[i_pattern][i_wire] != 0){
this_layer = pattern_envelope[0][i_wire];
this_wire = pattern_envelope[1+MESelection][i_wire]+key_wire;
Expand Down Expand Up @@ -896,7 +893,7 @@ bool CSCAnodeLCTProcessor::patternDetection(const int key_wire) {
std::multiset<int> mset_for_median;
mset_for_median.clear();

for (int i_wire = 0; i_wire < NUM_PATTERN_WIRES; i_wire++){
for (int i_wire = 0; i_wire < CSCConstants::MAX_WIRES_IN_PATTERN; i_wire++){
if (pattern_mask[i_pattern][i_wire] != 0){
this_layer = pattern_envelope[0][i_wire];
delta_wire = pattern_envelope[1+MESelection][i_wire];
Expand Down Expand Up @@ -1280,10 +1277,10 @@ void CSCAnodeLCTProcessor::lctSearch() {
plct != fourBest.end(); plct++) {

int bx = plct->getBX();
if (bx >= MAX_ALCT_BINS) {
if (bx >= CSCConstants::MAX_ALCT_TBINS) {
if (infoV > 0) edm::LogWarning("L1CSCTPEmulatorOutOfTimeALCT")
<< "+++ Bx of ALCT candidate, " << bx << ", exceeds max allowed, "
<< MAX_ALCT_BINS-1 << "; skipping it... +++\n";
<< CSCConstants::MAX_ALCT_TBINS-1 << "; skipping it... +++\n";
continue;
}

Expand All @@ -1300,22 +1297,22 @@ void CSCAnodeLCTProcessor::lctSearch() {

if (!isTMB07) {
// Prior to DAQ-2006 format, only ALCTs at the earliest bx were reported.
int first_bx = MAX_ALCT_BINS;
for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
int first_bx = CSCConstants::MAX_ALCT_TBINS;
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
if (bestALCT[bx].isValid()) {
first_bx = bx;
break;
}
}
if (first_bx < MAX_ALCT_BINS) {
for (int bx = first_bx + 1; bx < MAX_ALCT_BINS; bx++) {
if (first_bx < CSCConstants::MAX_ALCT_TBINS) {
for (int bx = first_bx + 1; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
if (bestALCT[bx].isValid()) bestALCT[bx].clear();
if (secondALCT[bx].isValid()) secondALCT[bx].clear();
}
}
}

for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
if (bestALCT[bx].isValid()) {
bestALCT[bx].setTrknmb(1);
if (infoV > 0) {
Expand Down Expand Up @@ -1347,7 +1344,7 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::bestTrackSelector(
const std::vector<CSCALCTDigi>& all_alcts) {
/* Selects two collision and two accelerator ALCTs per time bin with
the best quality. */
CSCALCTDigi bestALCTs[MAX_ALCT_BINS][2], secondALCTs[MAX_ALCT_BINS][2];
CSCALCTDigi bestALCTs[CSCConstants::MAX_ALCT_TBINS][2], secondALCTs[CSCConstants::MAX_ALCT_TBINS][2];

if (infoV > 1) {
LogTrace("CSCAnodeLCTProcessor") << all_alcts.size() <<
Expand All @@ -1359,7 +1356,7 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::bestTrackSelector(
}
}

CSCALCTDigi tA[MAX_ALCT_BINS][2], tB[MAX_ALCT_BINS][2];
CSCALCTDigi tA[CSCConstants::MAX_ALCT_TBINS][2], tB[CSCConstants::MAX_ALCT_TBINS][2];
for (std::vector <CSCALCTDigi>::const_iterator plct = all_alcts.begin();
plct != all_alcts.end(); plct++) {
if (!plct->isValid()) continue;
Expand Down Expand Up @@ -1389,7 +1386,7 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::bestTrackSelector(
}
}

for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
for (int accel = 0; accel <= 1; accel++) {
// Best ALCT is always tA.
if (tA[bx][accel].isValid()) {
Expand Down Expand Up @@ -1426,7 +1423,7 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::bestTrackSelector(

// Fill the vector with up to four best ALCTs per bx and return it.
std::vector<CSCALCTDigi> fourBest;
for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
for (int i = 0; i < 2; i++) {
if (bestALCTs[bx][i].isValid()) fourBest.push_back(bestALCTs[bx][i]);
}
Expand Down Expand Up @@ -1648,12 +1645,12 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::readoutALCTs() {
<< "; in-time ALCTs are not getting read-out!!! +++" << "\n";
}

if (late_tbins > MAX_ALCT_BINS-1) {
if (late_tbins > CSCConstants::MAX_ALCT_TBINS-1) {
if (infoV >= 0) edm::LogWarning("L1CSCTPEmulatorSuspiciousParameters")
<< "+++ Allowed range of time bins, [0-" << late_tbins
<< "] exceeds max allowed, " << MAX_ALCT_BINS-1 << " +++\n"
<< "] exceeds max allowed, " << CSCConstants::MAX_ALCT_TBINS-1 << " +++\n"
<< "+++ Set late_tbins to max allowed +++\n";
late_tbins = MAX_ALCT_BINS-1;
late_tbins = CSCConstants::MAX_ALCT_TBINS-1;
}
ifois = 1;
}
Expand Down Expand Up @@ -1692,7 +1689,7 @@ std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::readoutALCTs() {
// Returns vector of all found ALCTs, if any. Used in ALCT-CLCT matching.
std::vector<CSCALCTDigi> CSCAnodeLCTProcessor::getALCTs() {
std::vector<CSCALCTDigi> tmpV;
for (int bx = 0; bx < MAX_ALCT_BINS; bx++) {
for (int bx = 0; bx < CSCConstants::MAX_ALCT_TBINS; bx++) {
if (bestALCT[bx].isValid()) tmpV.push_back(bestALCT[bx]);
if (secondALCT[bx].isValid()) tmpV.push_back(secondALCT[bx]);
}
Expand All @@ -1713,7 +1710,7 @@ void CSCAnodeLCTProcessor::showPatterns(const int key_wire) {
strstrm_header << ((32-i)%10);
}
LogTrace("CSCAnodeLCTProcessor") << strstrm_header.str();
for (int i_wire = 0; i_wire < NUM_PATTERN_WIRES; i_wire++) {
for (int i_wire = 0; i_wire < CSCConstants::MAX_WIRES_IN_PATTERN; i_wire++) {
if (pattern_mask[i_pattern][i_wire] != 0) {
std::ostringstream strstrm_pulse;
int this_layer = pattern_envelope[0][i_wire];
Expand Down
24 changes: 10 additions & 14 deletions L1Trigger/CSCTriggerPrimitives/src/CSCAnodeLCTProcessor.h
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Expand Up @@ -15,7 +15,7 @@
*
* Updates for high pileup running by Vadim Khotilovich (TAMU), December 2012
*
* Updates for integrated local trigger with GEMs and RPCs by
* Updates for integrated local trigger with GEMs and RPCs by
* Sven Dildick (TAMU) and Tao Huang (TAMU), April 2015
*
* Removing usage of outdated class CSCTriggerGeometry by Sven Dildick (TAMU)
Expand Down Expand Up @@ -63,18 +63,15 @@ class CSCAnodeLCTProcessor
bool getDigis(const CSCWireDigiCollection* wiredc);
void getDigis(const CSCWireDigiCollection* wiredc, const CSCDetId& id);

/** Maximum number of time bins reported in the ALCT readout. */
enum {MAX_ALCT_BINS = 16};

/** Best LCTs in this chamber, as found by the processor.
In old ALCT algorithms, up to two best ALCT per Level-1 accept window
had been reported.
In the ALCT-2006 algorithms, up to two best ALCTs PER EVERY TIME BIN in
Level-1 accept window are reported. */
CSCALCTDigi bestALCT[MAX_ALCT_BINS];
CSCALCTDigi bestALCT[CSCConstants::MAX_ALCT_TBINS];

/** Second best LCTs in this chamber, as found by the processor. */
CSCALCTDigi secondALCT[MAX_ALCT_BINS];
CSCALCTDigi secondALCT[CSCConstants::MAX_ALCT_TBINS];

/** Returns vector of ALCTs in the read-out time window, if any. */
std::vector<CSCALCTDigi> readoutALCTs();
Expand All @@ -86,12 +83,11 @@ class CSCAnodeLCTProcessor
void setRing(unsigned r) {theRing = r;}

/** Pre-defined patterns. */
enum {NUM_PATTERN_WIRES = 14};
static const int pattern_envelope[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES];
static const int pattern_mask_slim[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES];
static const int pattern_mask_open[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES];
static const int pattern_mask_r1[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES];
static const int time_weights[NUM_PATTERN_WIRES];
static const int pattern_envelope[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN];
static const int pattern_mask_slim[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN];
static const int pattern_mask_open[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN];
static const int pattern_mask_r1[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN];
static const int time_weights[CSCConstants::MAX_WIRES_IN_PATTERN];

private:
/** Verbosity level: 0: no print (default).
Expand Down Expand Up @@ -152,7 +148,7 @@ class CSCAnodeLCTProcessor
/** SLHC: delta BX time depth for ghostCancellationLogic */
int ghost_cancellation_bx_depth;

/** SLHC: whether to consider ALCT candidates' qualities
/** SLHC: whether to consider ALCT candidates' qualities
while doing ghostCancellationLogic on +-1 wire groups */
bool ghost_cancellation_side_quality;

Expand Down Expand Up @@ -181,7 +177,7 @@ class CSCAnodeLCTProcessor
static const unsigned int def_l1a_window_width;

/** Chosen pattern mask. */
int pattern_mask[CSCConstants::NUM_ALCT_PATTERNS][NUM_PATTERN_WIRES];
int pattern_mask[CSCConstants::NUM_ALCT_PATTERNS][CSCConstants::MAX_WIRES_IN_PATTERN];

/** Load pattern mask defined by configuration into pattern_mask */
void loadPatternMask();
Expand Down