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Pull requests: llvm/circt

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Pull requests list

[SV][ExportVerilog] Add sv.func, sv.func.call{.procedural}, sv.func.dpi.import
#6977 opened May 1, 2024 by uenoku • Draft
2
[SMT] Added support for :pattern attribute
#6976 opened May 1, 2024 by luisacicolini Loading…
28
[firtool] Integrate AssertProperty lowering into BTOR2 pipeline
#6975 opened Apr 30, 2024 by dobios Loading…
[FIRRTL] Output directory control for layers and modules
#6971 opened Apr 30, 2024 by rwy7 • Draft
1
[NFCI] Document division and the rational for the handling of divide by zero
#6962 opened Apr 29, 2024 by darthscsi Loading…
9
[Comb] Officialize support for zero-width integers
#6959 opened Apr 28, 2024 by Moxinilian Loading…
6
[LLHD] Replace entity with module
LLHD
#6958 opened Apr 28, 2024 by maerhart • Draft
[HWToLLVM][Arc] Add out-of-bounds handler for array accesses
Arc Involving the `arc` dialect
#6956 opened Apr 26, 2024 by fzi-hielscher • Draft
1
SCF To Calyx Support Float Add and Float SeqMemory Read/Write
#6953 opened Apr 25, 2024 by jiahanxie353 • Draft
7
Pipeline For Lowering PyTorch Tensor Add To FPGA
#6952 opened Apr 25, 2024 by jiahanxie353 Loading…
8
[ImportVerilog] Add conditional operator.
Verilog/SystemVerilog Involving a Verilog dialect
#6950 opened Apr 25, 2024 by angelzzzzz Loading…
6
[CombToArith] Fix coarsening of division by zero UB
Arc Involving the `arc` dialect
#6945 opened Apr 23, 2024 by maerhart Loading…
1
4
[DC] Add merge lowering
#6943 opened Apr 22, 2024 by mortbopet Loading…
3
[HandshakeToDC] Add pack/unpack lowering patterns
DC Handshake
#6941 opened Apr 22, 2024 by mortbopet Loading…
6
[FIRRTL,PASS] Simple module summary looking for likely to dedup larger or numerous modules. This is to guide developers in using chisel better.
#6935 opened Apr 19, 2024 by darthscsi Loading…
10
[Handshake] Add merge decomposition pattern
Handshake
#6934 opened Apr 19, 2024 by mortbopet Loading…
5
[HW] Rework InnerSym infra to support nested symbol tables
#6933 opened Apr 19, 2024 by mortbopet Loading…
80
[FIRRTL] Make input probes illegal
#6921 opened Apr 16, 2024 by dtzSiFive • Draft
4
[FIRRTL] Add debug logging to dedup
#6916 opened Apr 12, 2024 by jackkoenig Loading…
14
[FIRRTL][LowerIntrinsics] Add stat and preserve if no changes.
#6911 opened Apr 10, 2024 by dtzSiFive Loading…
3
[FIRRTL] Use lower-sigs to handle port scalarization of internal modules. This removes Lower Types from dealing with it in anticipation of Lower Types being simplified.
#6904 opened Apr 8, 2024 by darthscsi • Draft
1
[InferReadWrite] Update the heuristic to infer the enable signal
#6862 opened Mar 21, 2024 by prithayan Loading…
1
[Seq] Enforce non-negative preset values in FirRegOp printer/parser
#6856 opened Mar 20, 2024 by fzi-hielscher Loading…
4
[Arc] Add basic support for assert operation.
#6839 opened Mar 17, 2024 by elhewaty Loading…
2 tasks
1
30
[CheckCombLoops] Handle RWProbeOp
#6824 opened Mar 13, 2024 by prithayan Loading…
1
7
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