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Merge branch 'master' of https://github.com/pyr0ball/pyr0piezo into d…
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pyr0ball committed Nov 7, 2019
2 parents 9ae410f + cd3503b commit 6455054
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6,047 changes: 6,000 additions & 47 deletions Eagle_Files/EasyPiezi/EasyPiezi_2.2.0.brd
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141 changes: 71 additions & 70 deletions Eagle_Files/EasyPiezi/EasyPiezi_2.2.0.sch
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Expand Up @@ -6,7 +6,7 @@
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Expand Down Expand Up @@ -581,18 +581,6 @@
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<pad name="B5,5" x="0" y="0" drill="5.5" diameter="9"/>
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<description>Chip, 2.00 X 1.25 X 1.30 mm body
&lt;p&gt;Chip package with body size 2.00 X 1.25 X 1.30 mm&lt;/p&gt;</description>
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<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 0603 reflow solder&lt;/b&gt;&lt;p&gt;
Metric Code Size 1608</description>
Expand Down Expand Up @@ -1101,46 +1089,6 @@ Metric Code Size 1608</description>
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</package>
<package name="SSOP14" urn="urn:adsk.eagle:footprint:16141/1" library_version="58" library_locally_modified="yes">
<description>&lt;b&gt;Small Shrink Outline Package&lt;/b&gt;</description>
<wire x1="-2.243" y1="2.145" x2="2.243" y2="2.145" width="0.2032" layer="21"/>
Expand Down Expand Up @@ -2099,6 +2047,59 @@ https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10104320.pdf</descripti
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<package name="CAPC2012X130" urn="urn:adsk.eagle:footprint:5225118/3" library_version="113" library_locally_modified="yes">
<description>Chip, 2.00 X 1.25 X 1.30 mm body
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<text x="0" y="0.9949" size="0.6096" layer="25" font="vector" ratio="11" align="bottom-center">&gt;NAME</text>
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<description>&lt;b&gt;Small Outline Package 14&lt;/b&gt;</description>
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<text x="-4.572" y="-1.905" size="1.27" layer="25" rot="R90">&gt;NAME</text>
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</package>
</packages>
<packages3d>
<package3d name="SOT23" urn="urn:adsk.eagle:package:6899267/2" type="model" library_version="80">
Expand Down Expand Up @@ -2194,13 +2195,6 @@ https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10104320.pdf</descripti
<packageinstance name="HOLES_5,5-PAD"/>
</packageinstances>
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<package3d name="CAPC2012X130" urn="urn:adsk.eagle:package:5225034/2" type="model" library_version="12" library_locally_modified="yes">
<description>Chip, 2.00 X 1.25 X 1.30 mm body
&lt;p&gt;Chip package with body size 2.00 X 1.25 X 1.30 mm&lt;/p&gt;</description>
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<packageinstance name="CAPC2012X130"/>
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<package3d name="C0603K" urn="urn:adsk.eagle:package:5710321/1" type="model" library_version="12" library_locally_modified="yes">
<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 0603 reflow solder&lt;/b&gt;&lt;p&gt;
Metric Code Size 1608</description>
Expand Down Expand Up @@ -2491,12 +2485,6 @@ Metric Code Size 1608</description>
<packageinstance name="DIL14"/>
</packageinstances>
</package3d>
<package3d name="SO14" urn="urn:adsk.eagle:package:16406/2" type="model" library_version="58" library_locally_modified="yes">
<description>Small Outline Package 14</description>
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<packageinstance name="SO14"/>
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<package3d name="SSOP14" urn="urn:adsk.eagle:package:16412/2" type="model" library_version="58" library_locally_modified="yes">
<description>Small Shrink Outline Package</description>
<packageinstances>
Expand Down Expand Up @@ -2639,6 +2627,19 @@ https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10104320.pdf</descripti
<packageinstance name="53398-03"/>
</packageinstances>
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<description>Chip, 2.00 X 1.25 X 1.30 mm body
&lt;p&gt;Chip package with body size 2.00 X 1.25 X 1.30 mm&lt;/p&gt;</description>
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<packageinstance name="CAPC2012X130"/>
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<package3d name="SO14" urn="urn:adsk.eagle:package:14923493/1" type="model" library_version="113" library_locally_modified="yes">
<description>&lt;b&gt;Small Outline Package 14&lt;/b&gt;</description>
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<packageinstance name="SO14"/>
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</packages3d>
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<symbol name="KA2KA" urn="urn:adsk.eagle:symbol:6897169/1" library_version="1" library_locally_modified="yes">
Expand Down Expand Up @@ -3335,7 +3336,7 @@ wire to board 1.25 mm (.049 inch) pitch header</description>
</device>
</devices>
</deviceset>
<deviceset name="SEEED-CAPACITOR_CERAMIC-10UF-25V-10%-X5R(0805)" urn="urn:adsk.eagle:component:6973862/1" prefix="C" uservalue="yes" library_version="14">
<deviceset name="SEEED-CAPACITOR_CERAMIC-10UF-25V-10%-X5R(0805)" urn="urn:adsk.eagle:component:6973862/2" prefix="C" uservalue="yes" library_version="113" library_locally_modified="yes">
<description>302010178</description>
<gates>
<gate name="G$1" symbol="SEEED-CAPACITOR_C" x="0" y="0"/>
Expand All @@ -3347,7 +3348,7 @@ wire to board 1.25 mm (.049 inch) pitch header</description>
<connect gate="G$1" pin="2" pad="2"/>
</connects>
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<package3dinstance package3d_urn="urn:adsk.eagle:package:5225034/2"/>
<package3dinstance package3d_urn="urn:adsk.eagle:package:5225034/3"/>
</package3dinstances>
<technologies>
<technology name=""/>
Expand Down Expand Up @@ -4120,7 +4121,7 @@ wire to board 1.25 mm (.049 inch) pitch header</description>
</device>
</devices>
</deviceset>
<deviceset name="LM2902" urn="urn:adsk.eagle:component:8766129/3" prefix="U" library_version="109">
<deviceset name="LM2902" urn="urn:adsk.eagle:component:8766129/4" prefix="U" library_version="113" library_locally_modified="yes">
<description>&lt;b&gt;Low power quad operational amplifier&lt;/b&gt;&lt;p&gt;
Source: &lt;a href="http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000533.pdf"&gt; Data sgeet &lt;/a&gt;</description>
<gates>
Expand Down Expand Up @@ -4173,7 +4174,7 @@ Source: &lt;a href="http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL
<connect gate="P" pin="V-" pad="11"/>
</connects>
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<package3dinstance package3d_urn="urn:adsk.eagle:package:16406/2"/>
<package3dinstance package3d_urn="urn:adsk.eagle:package:14923493/1"/>
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<technologies>
<technology name=""/>
Expand Down
40 changes: 28 additions & 12 deletions Eagle_Files/PiezoDisk-PCB/Pyr0-Piezo_SingleDisk_Adapter.brd
View file
Expand Up @@ -6,7 +6,7 @@
<setting alwaysvectorfont="yes"/>
<setting verticaltext="up"/>
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<layer number="2" name="Route2" color="16" fill="1" visible="no" active="no"/>
Expand Down Expand Up @@ -171,18 +171,34 @@
</layers>
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<wire x1="-1.27" y1="-3.429" x2="-1.27" y2="-1.651" width="0" layer="20"/>
<wire x1="-1.27" y1="-1.651" x2="-1.397" y2="-1.524" width="0" layer="20"/>
<wire x1="-1.397" y1="-1.524" x2="-0.889" y2="1.905" width="0" layer="20" curve="-106.853992"/>
<wire x1="-10.795" y1="-3.06" x2="-6.775" y2="2.21" width="0" layer="20" curve="-75.323607"/>
<wire x1="10.775" y1="-3.06" x2="6.775" y2="2.21" width="0" layer="20" curve="75.323607"/>
</plain>
<libraries>
<library name="PiezoFFC" urn="urn:adsk.eagle:library:6897166">
Expand Down Expand Up @@ -322,7 +338,7 @@
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<designrules name="default">
<designrules name="default *">
<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
&lt;p&gt;
Die Standard-Design-Rules sind so gewählt, dass sie für
Expand Down Expand Up @@ -394,7 +410,7 @@ design rules under a new name.</description>
<param name="srRoundness" value="0"/>
<param name="srMinRoundness" value="0mil"/>
<param name="srMaxRoundness" value="0mil"/>
<param name="slThermalIsolate" value="10mil"/>
<param name="slThermalIsolate" value="6mil"/>
<param name="slThermalsForVias" value="0"/>
<param name="dpMaxLengthDifference" value="10mm"/>
<param name="dpGapFactor" value="2.5"/>
Expand Down Expand Up @@ -532,7 +548,7 @@ design rules under a new name.</description>
<contactref element="PZ1" pad="GND2"/>
<contactref element="PZ1" pad="GND3"/>
<contactref element="PZ1" pad="GND4"/>
<polygon width="0" layer="1">
<polygon width="0.254" layer="1">
<vertex x="-10.795" y="0.94"/>
<vertex x="-10.795" y="-17.78"/>
<vertex x="10.775" y="-17.78"/>
Expand All @@ -542,7 +558,7 @@ design rules under a new name.</description>
<vertex x="-1.27" y="1.905"/>
<vertex x="-2.235" y="0.94"/>
</polygon>
<polygon width="0" layer="16">
<polygon width="0.254" layer="16">
<vertex x="-10.795" y="0.94"/>
<vertex x="-10.795" y="-17.78"/>
<vertex x="10.775" y="-17.78"/>
Expand Down

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