Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
hls		hls
verilog-sv		verilog-sv
vhdl		vhdl
.gitignore		.gitignore
README.md		README.md

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FPGA Lab

This repo includes the designs that I am currently learning or have learned in the past.

Table of Contents

SystemVerilog/Verilog

Lab #	Topic	Description	Status
S1	FIFO Design	Everything related to FIFO design	🚧

VHDL

Lab #	Topic	Description	Status
V1	FIFO Design	Everything related to FIFO design	📌

HLS

Lab #	Topic	Description	Status
H1	FIFO Design	Everything related to FIFO design	📌

SystemVerilog/Verilog

This directory contains all SystemVerilog and Verilog labs.

VHDL

This directory contains all VHDL labs.

HLS

This directory contains all HLS labs.

About

This is the repo for keeping track of all my FPGA learning activities.

fpga hls vhdl verilog systemverilog

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